* [PATCH 1/2] drm/i915: IVB/HSW have 32 fence register @ 2013-04-09 8:45 ville.syrjala 2013-04-09 8:45 ` [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+ ville.syrjala 2013-04-09 10:02 ` [PATCH v2] drm/i915: IVB/HSW have 32 fence register ville.syrjala 0 siblings, 2 replies; 7+ messages in thread From: ville.syrjala @ 2013-04-09 8:45 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Increase the number of fence registers to 32 on IVB/HSW. VLV however only has 16 fence registers according to the docs. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 6 +++--- drivers/gpu/drm/i915/i915_gem.c | 4 +++- drivers/gpu/drm/i915/i915_irq.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 69ddfd1..fa8ca2f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -195,9 +195,9 @@ struct drm_i915_master_private { struct _drm_i915_sarea *sarea_priv; }; #define I915_FENCE_REG_NONE -1 -#define I915_MAX_NUM_FENCES 16 -/* 16 fences + sign bit for FENCE_REG_NONE */ -#define I915_MAX_NUM_FENCE_BITS 5 +#define I915_MAX_NUM_FENCES 32 +/* 32 fences + sign bit for FENCE_REG_NONE */ +#define I915_MAX_NUM_FENCE_BITS 6 struct drm_i915_fence_reg { struct list_head lru_list; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 63c05dd..211ce8f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4184,7 +4184,9 @@ i915_gem_load(struct drm_device *dev) if (!drm_core_check_feature(dev, DRIVER_MODESET)) dev_priv->fence_reg_start = 3; - if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) + if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) + dev_priv->num_fence_regs = 32; + else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) dev_priv->num_fence_regs = 16; else dev_priv->num_fence_regs = 8; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index fc35d52..985d1f5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1217,7 +1217,7 @@ static void i915_gem_record_fences(struct drm_device *dev, switch (INTEL_INFO(dev)->gen) { case 7: case 6: - for (i = 0; i < 16; i++) + for (i = 0; i < dev_priv->num_fence_regs; i++) error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); break; case 5: -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+ 2013-04-09 8:45 [PATCH 1/2] drm/i915: IVB/HSW have 32 fence register ville.syrjala @ 2013-04-09 8:45 ` ville.syrjala 2013-04-09 11:54 ` Daniel Vetter 2013-04-09 10:02 ` [PATCH v2] drm/i915: IVB/HSW have 32 fence register ville.syrjala 1 sibling, 1 reply; 7+ messages in thread From: ville.syrjala @ 2013-04-09 8:45 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> BSpec contains several scattered notes which state that the maximum fence stride was increased to 256KB on IVB. Testing on real hardware agrees. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_tiling.c | 9 ++++++--- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index c807eb9..139d17d 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) tile_width = 512; /* check maximum stride & object size */ - if (INTEL_INFO(dev)->gen >= 4) { - /* i965 stores the end address of the gtt mapping in the fence - * reg, so dont bother to check the size */ + /* i965+ stores the end address of the gtt mapping in the fence + * reg, so dont bother to check the size */ + if (INTEL_INFO(dev)->gen >= 7) { + if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) + return false; + } else if (INTEL_INFO(dev)->gen >= 4) { if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) return false; } else { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0e4b7fb..ec4e054 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -424,6 +424,7 @@ #define FENCE_REG_SANDYBRIDGE_0 0x100000 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 +#define GEN7_FENCE_MAX_PITCH_VAL 0x0800 /* control register for cpu gtt access */ #define TILECTL 0x101000 -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+ 2013-04-09 8:45 ` [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+ ville.syrjala @ 2013-04-09 11:54 ` Daniel Vetter 2013-04-09 12:03 ` Ville Syrjälä 0 siblings, 1 reply; 7+ messages in thread From: Daniel Vetter @ 2013-04-09 11:54 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Tue, Apr 09, 2013 at 11:45:05AM +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > BSpec contains several scattered notes which state that the maximum > fence stride was increased to 256KB on IVB. > > Testing on real hardware agrees. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_gem_tiling.c | 9 ++++++--- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c > index c807eb9..139d17d 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > @@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) > tile_width = 512; > > /* check maximum stride & object size */ > - if (INTEL_INFO(dev)->gen >= 4) { > - /* i965 stores the end address of the gtt mapping in the fence > - * reg, so dont bother to check the size */ > + /* i965+ stores the end address of the gtt mapping in the fence > + * reg, so dont bother to check the size */ > + if (INTEL_INFO(dev)->gen >= 7) { I've thought that his does not apply to vlv? Or has that now changed? -Daniel > + if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) > + return false; > + } else if (INTEL_INFO(dev)->gen >= 4) { > if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) > return false; > } else { > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0e4b7fb..ec4e054 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -424,6 +424,7 @@ > > #define FENCE_REG_SANDYBRIDGE_0 0x100000 > #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 > +#define GEN7_FENCE_MAX_PITCH_VAL 0x0800 > > /* control register for cpu gtt access */ > #define TILECTL 0x101000 > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+ 2013-04-09 11:54 ` Daniel Vetter @ 2013-04-09 12:03 ` Ville Syrjälä 2013-04-09 18:16 ` Daniel Vetter 0 siblings, 1 reply; 7+ messages in thread From: Ville Syrjälä @ 2013-04-09 12:03 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx On Tue, Apr 09, 2013 at 01:54:01PM +0200, Daniel Vetter wrote: > On Tue, Apr 09, 2013 at 11:45:05AM +0300, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > BSpec contains several scattered notes which state that the maximum > > fence stride was increased to 256KB on IVB. > > > > Testing on real hardware agrees. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_gem_tiling.c | 9 ++++++--- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > 2 files changed, 7 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c > > index c807eb9..139d17d 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > > @@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) > > tile_width = 512; > > > > /* check maximum stride & object size */ > > - if (INTEL_INFO(dev)->gen >= 4) { > > - /* i965 stores the end address of the gtt mapping in the fence > > - * reg, so dont bother to check the size */ > > + /* i965+ stores the end address of the gtt mapping in the fence > > + * reg, so dont bother to check the size */ > > + if (INTEL_INFO(dev)->gen >= 7) { > > I've thought that his does not apply to vlv? Or has that now changed? The docs are telling me that VLV also has 256KB max stride. > -Daniel > > > + if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) > > + return false; > > + } else if (INTEL_INFO(dev)->gen >= 4) { > > if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) > > return false; > > } else { > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 0e4b7fb..ec4e054 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -424,6 +424,7 @@ > > > > #define FENCE_REG_SANDYBRIDGE_0 0x100000 > > #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 > > +#define GEN7_FENCE_MAX_PITCH_VAL 0x0800 > > > > /* control register for cpu gtt access */ > > #define TILECTL 0x101000 > > -- > > 1.8.1.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Ville Syrjälä Intel OTC ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+ 2013-04-09 12:03 ` Ville Syrjälä @ 2013-04-09 18:16 ` Daniel Vetter 0 siblings, 0 replies; 7+ messages in thread From: Daniel Vetter @ 2013-04-09 18:16 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx On Tue, Apr 09, 2013 at 03:03:28PM +0300, Ville Syrjälä wrote: > On Tue, Apr 09, 2013 at 01:54:01PM +0200, Daniel Vetter wrote: > > On Tue, Apr 09, 2013 at 11:45:05AM +0300, ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > BSpec contains several scattered notes which state that the maximum > > > fence stride was increased to 256KB on IVB. > > > > > > Testing on real hardware agrees. > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_gem_tiling.c | 9 ++++++--- > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > 2 files changed, 7 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c > > > index c807eb9..139d17d 100644 > > > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > > > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > > > @@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) > > > tile_width = 512; > > > > > > /* check maximum stride & object size */ > > > - if (INTEL_INFO(dev)->gen >= 4) { > > > - /* i965 stores the end address of the gtt mapping in the fence > > > - * reg, so dont bother to check the size */ > > > + /* i965+ stores the end address of the gtt mapping in the fence > > > + * reg, so dont bother to check the size */ > > > + if (INTEL_INFO(dev)->gen >= 7) { > > > > I've thought that his does not apply to vlv? Or has that now changed? > > The docs are telling me that VLV also has 256KB max stride. Queued for -next, thanks for the patch. -Daniel > > > -Daniel > > > > > + if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) > > > + return false; > > > + } else if (INTEL_INFO(dev)->gen >= 4) { > > > if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) > > > return false; > > > } else { > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index 0e4b7fb..ec4e054 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -424,6 +424,7 @@ > > > > > > #define FENCE_REG_SANDYBRIDGE_0 0x100000 > > > #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 > > > +#define GEN7_FENCE_MAX_PITCH_VAL 0x0800 > > > > > > /* control register for cpu gtt access */ > > > #define TILECTL 0x101000 > > > -- > > > 1.8.1.5 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > > -- > Ville Syrjälä > Intel OTC -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2] drm/i915: IVB/HSW have 32 fence register 2013-04-09 8:45 [PATCH 1/2] drm/i915: IVB/HSW have 32 fence register ville.syrjala 2013-04-09 8:45 ` [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+ ville.syrjala @ 2013-04-09 10:02 ` ville.syrjala 2013-04-11 18:23 ` Daniel Vetter 1 sibling, 1 reply; 7+ messages in thread From: ville.syrjala @ 2013-04-09 10:02 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Increase the number of fence registers to 32 on IVB/HSW. VLV however only has 16 fence registers according to the docs. Increasing the number of fences was attempted before [1], but there was some uncertainty about the maximum CPU fence number for FBC. Since then BSpec has been updated to state that there are in fact 32 fence registers, and the CPU fence number field in the SNB_DPFC_CTL_SA register is 5 bits, and the CPU fence number field in the ILK_DPFC_CONTROL register must be zero. So now it all makes sense. [1] http://lists.freedesktop.org/archives/intel-gfx/2011-October/012865.html v2: Include some background information based on the previous attempt Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 6 +++--- drivers/gpu/drm/i915/i915_gem.c | 4 +++- drivers/gpu/drm/i915/i915_irq.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 69ddfd1..fa8ca2f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -195,9 +195,9 @@ struct drm_i915_master_private { struct _drm_i915_sarea *sarea_priv; }; #define I915_FENCE_REG_NONE -1 -#define I915_MAX_NUM_FENCES 16 -/* 16 fences + sign bit for FENCE_REG_NONE */ -#define I915_MAX_NUM_FENCE_BITS 5 +#define I915_MAX_NUM_FENCES 32 +/* 32 fences + sign bit for FENCE_REG_NONE */ +#define I915_MAX_NUM_FENCE_BITS 6 struct drm_i915_fence_reg { struct list_head lru_list; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 63c05dd..211ce8f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4184,7 +4184,9 @@ i915_gem_load(struct drm_device *dev) if (!drm_core_check_feature(dev, DRIVER_MODESET)) dev_priv->fence_reg_start = 3; - if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) + if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) + dev_priv->num_fence_regs = 32; + else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) dev_priv->num_fence_regs = 16; else dev_priv->num_fence_regs = 8; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index fc35d52..985d1f5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1217,7 +1217,7 @@ static void i915_gem_record_fences(struct drm_device *dev, switch (INTEL_INFO(dev)->gen) { case 7: case 6: - for (i = 0; i < 16; i++) + for (i = 0; i < dev_priv->num_fence_regs; i++) error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); break; case 5: -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2] drm/i915: IVB/HSW have 32 fence register 2013-04-09 10:02 ` [PATCH v2] drm/i915: IVB/HSW have 32 fence register ville.syrjala @ 2013-04-11 18:23 ` Daniel Vetter 0 siblings, 0 replies; 7+ messages in thread From: Daniel Vetter @ 2013-04-11 18:23 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Tue, Apr 09, 2013 at 01:02:47PM +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Increase the number of fence registers to 32 on IVB/HSW. VLV however > only has 16 fence registers according to the docs. > > Increasing the number of fences was attempted before [1], but there was > some uncertainty about the maximum CPU fence number for FBC. Since then > BSpec has been updated to state that there are in fact 32 fence registers, > and the CPU fence number field in the SNB_DPFC_CTL_SA register is 5 bits, > and the CPU fence number field in the ILK_DPFC_CONTROL register must be > zero. So now it all makes sense. > > [1] http://lists.freedesktop.org/archives/intel-gfx/2011-October/012865.html > > v2: Include some background information based on the previous attempt > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-04-11 18:20 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-04-09 8:45 [PATCH 1/2] drm/i915: IVB/HSW have 32 fence register ville.syrjala 2013-04-09 8:45 ` [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+ ville.syrjala 2013-04-09 11:54 ` Daniel Vetter 2013-04-09 12:03 ` Ville Syrjälä 2013-04-09 18:16 ` Daniel Vetter 2013-04-09 10:02 ` [PATCH v2] drm/i915: IVB/HSW have 32 fence register ville.syrjala 2013-04-11 18:23 ` Daniel Vetter
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