diff for duplicates of <20130416134856.GB30292@arm.com> diff --git a/a/1.txt b/N1/1.txt index d7af1dd..c18b16b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,7 +4,7 @@ On Tue, Apr 16, 2013 at 01:58:27PM +0100, Rob Herring wrote: > >> On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring <robherring2@gmail.com> wrote: > >>> Exclusive accesses still have further restrictions. From section 3.4.5: > >>> -> >>> ? It is IMPLEMENTATION DEFINED whether LDREX and STREX operations can be +> >>> • It is IMPLEMENTATION DEFINED whether LDREX and STREX operations can be > >>> performed to a memory region > >>> with the Device or Strongly-ordered memory attribute. Unless the > >>> implementation documentation explicitly diff --git a/a/content_digest b/N1/content_digest index a8756d6..1d5597a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -6,10 +6,18 @@ "ref\0CAMbhsRRT7tOBHppvjJEW5wRtVaUhwxr8=YQY=Sy0VAFeBg1JmQ@mail.gmail.com\0" "ref\020130416084418.GA30756@mudshark.cambridge.arm.com\0" "ref\0516D4AF3.5060205@gmail.com\0" - "From\0catalin.marinas@arm.com (Catalin Marinas)\0" - "Subject\0[RFC PATCH 1/3] pstore-ram: use write-combine mappings\0" + "From\0Catalin Marinas <catalin.marinas@arm.com>\0" + "Subject\0Re: [RFC PATCH 1/3] pstore-ram: use write-combine mappings\0" "Date\0Tue, 16 Apr 2013 14:48:56 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Rob Herring <robherring2@gmail.com>\0" + "Cc\0Will Deacon <Will.Deacon@arm.com>" + Colin Cross <ccross@android.com> + lkml <linux-kernel@vger.kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + rob.herring@calxeda.com <rob.herring@calxeda.com> + Anton Vorontsov <cbouatmailru@gmail.com> + Kees Cook <keescook@chromium.org> + " Tony Luck <tony.luck@intel.com>\0" "\00:1\0" "b\0" "On Tue, Apr 16, 2013 at 01:58:27PM +0100, Rob Herring wrote:\n" @@ -18,7 +26,7 @@ "> >> On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring <robherring2@gmail.com> wrote:\n" "> >>> Exclusive accesses still have further restrictions. From section 3.4.5:\n" "> >>>\n" - "> >>> ? It is IMPLEMENTATION DEFINED whether LDREX and STREX operations can be\n" + "> >>> \342\200\242 It is IMPLEMENTATION DEFINED whether LDREX and STREX operations can be\n" "> >>> performed to a memory region\n" "> >>> with the Device or Strongly-ordered memory attribute. Unless the\n" "> >>> implementation documentation explicitly\n" @@ -52,4 +60,4 @@ "-- \n" Catalin -02f3f96b39bb76ec1e0fe4e89eee8941f75c623bb9271233390fe3cc20313991 +9c723b8ef79f27129f903454343bad51b64553b37fb60502763259c339412fa6
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