From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 1/4] drm/i915: Disable primary plane trickle
 feed for g4x
Date: Wed, 17 Apr 2013 20:46:48 +0300
Message-ID: <20130417174647.GP4469@intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
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On Wed, Apr 17, 2013 at 06:25:29PM +0100, Chris Wilson wrote:
> On Wed, Apr 17, 2013 at 08:11:58PM +0300, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > The docs say that the trickle feed disable bit is present (for primary
> > planes only, not video sprites) on BLC and CTG, and that it must be set
> > for ELK. Just set it for all g4x chipset.
> > =

> > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> =

> I'm stunned that we did all the post-pch chipsets but missed g4x.
> Perhaps we should also do it during init_clock_gating() as we do for
> other generations?

Actually we do it in both ironlake_update_plane() and
init_clock_gating() for gen5+. I guess someone wanted to make sure
the bit sticks ;)

I'm thinking I'd rather kill the init_clock_gating() parts since that
would keep the whole plane setup in one place.

-- =

Ville Syrj=E4l=E4
Intel OTC