From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: implement high-bpc + pipeconf-dither support for g4x/vlv Date: Wed, 24 Apr 2013 14:07:35 +0300 Message-ID: <20130424110735.GI4469@intel.com> References: <20130419093911.4b4e72dc@jbarnes-desktop> <1366395430-7365-1-git-send-email-daniel.vetter@ffwll.ch> <20130423152754.GH4469@intel.com> <20130423203935.GK6169@phenom.ffwll.local> <20130423222759.GL6169@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id E3FB3E637F for ; Wed, 24 Apr 2013 04:07:39 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130423222759.GL6169@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 24, 2013 at 12:27:59AM +0200, Daniel Vetter wrote: > On Tue, Apr 23, 2013 at 10:39:35PM +0200, Daniel Vetter wrote: > > On Tue, Apr 23, 2013 at 06:27:54PM +0300, Ville Syrj=E4l=E4 wrote: > > > The g4x docs are a bit confusing though. They seem to indicate the the > > > PIPECONF dither controls only affect DP. > > = > > Hm, this could put a pending question from Jesse at ease whether we sho= uld > > still enable dithering in the lvds port register on g4x. Can you point = me > > at the relevant bspec language? I didn't spot anything when hunting aro= und > > in the docs ... > = > Hm, I've done some testing and the pipeconf dithering seems to indeed have > no effect on the lvds panel. I've gotten away since this patch didn't > clear that bit correctly. I'll update the patch. If you can dig out the > Bspec reference, that'd still be great. It's mentioned in the PIPECONF description. "4 | Dithering enable [DevCTG]: This bit enables dithering for DisplayPor= t 6bpc or 8bpc modes" "3:2 | Dithering type [DevCTG]: This bit selects dithering type for Display= Port 6bpc or 8bpc modes" Also the description of "7:5 | Bits Per Color [DevCTG]" also talks a lot ab= out DP, which maybe implies that it too only affects DP. For SDVO/HDMI the port register anyway only has 8bpc support so I guess that's covered, but I'm not sure what the deal is with the CRT output. -- = Ville Syrj=E4l=E4 Intel OTC