From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 10/15] drm/i915: split up fdi_set_m_n into computation and hw setup Date: Wed, 24 Apr 2013 14:26:45 +0300 Message-ID: <20130424112645.GM4469@intel.com> References: <1366363487-15926-1-git-send-email-daniel.vetter@ffwll.ch> <1366363487-15926-11-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E854E63A2 for ; Wed, 24 Apr 2013 04:27:16 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1366363487-15926-11-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Fri, Apr 19, 2013 at 11:24:42AM +0200, Daniel Vetter wrote: > And also move the computed m_n values into the pipe_config. This is a > prep step to move the fdi state computation completely into the > prepare phase of the modeset sequence. Which will allow us to handle > fdi link bw constraints in a better way. > = > Signed-off-by: Daniel Vetter Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++----------- > drivers/gpu/drm/i915/intel_drv.h | 3 ++- > 2 files changed, 17 insertions(+), 12 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index b7774c1..7abcd60 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5480,13 +5480,11 @@ void intel_cpu_transcoder_set_m_n(struct intel_cr= tc *crtc, > } > } > = > -static void ironlake_fdi_set_m_n(struct drm_crtc *crtc) > +static void ironlake_fdi_compute_config(struct intel_crtc *intel_crtc) > { > - struct drm_device *dev =3D crtc->dev; > - struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > + struct drm_device *dev =3D intel_crtc->base.dev; > struct drm_display_mode *adjusted_mode =3D > &intel_crtc->config.adjusted_mode; > - struct intel_link_m_n m_n =3D {0}; > int target_clock, lane, link_bw; > = > /* FDI is a binary signal running at ~2.7GHz, encoding > @@ -5511,9 +5509,7 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *c= rtc) > if (intel_crtc->config.pixel_multiplier > 1) > link_bw *=3D intel_crtc->config.pixel_multiplier; > intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock, > - link_bw, &m_n); > - > - intel_cpu_transcoder_set_m_n(intel_crtc, &m_n); > + link_bw, &intel_crtc->config.fdi_m_n); > } > = > static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) > @@ -5735,8 +5731,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc = *crtc, > /* Note, this also computes intel_crtc->fdi_lanes which is used below in > * ironlake_check_fdi_lanes. */ > intel_crtc->config.fdi_lanes =3D 0; > - if (intel_crtc->config.has_pch_encoder) > - ironlake_fdi_set_m_n(crtc); > + if (intel_crtc->config.has_pch_encoder) { > + ironlake_fdi_compute_config(intel_crtc); > + > + intel_cpu_transcoder_set_m_n(intel_crtc, > + &intel_crtc->config.fdi_m_n); > + } > = > fdi_config_ok =3D ironlake_check_fdi_lanes(intel_crtc); > = > @@ -5866,8 +5866,12 @@ static int haswell_crtc_mode_set(struct drm_crtc *= crtc, > = > intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); > = > - if (intel_crtc->config.has_pch_encoder) > - ironlake_fdi_set_m_n(crtc); > + if (intel_crtc->config.has_pch_encoder) { > + ironlake_fdi_compute_config(intel_crtc); > + > + intel_cpu_transcoder_set_m_n(intel_crtc, > + &intel_crtc->config.fdi_m_n); > + } > = > haswell_set_pipeconf(crtc); > = > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/inte= l_drv.h > index 179b42b..f40b43f 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -230,8 +230,9 @@ struct intel_crtc_config { > /* Used by SDVO (and if we ever fix it, HDMI). */ > unsigned pixel_multiplier; > = > - /* FDI lanes used, only valid if has_pch_encoder is set. */ > + /* FDI configuration, only valid if has_pch_encoder is set. */ > int fdi_lanes; > + struct intel_link_m_n fdi_m_n; > }; > = > struct intel_crtc { > -- = > 1.7.11.7 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC