From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 09/15] drm/i915: hw state readout support for pipe_config->fdi_lanes Date: Wed, 24 Apr 2013 14:49:38 +0200 Message-ID: <20130424124938.GR6169@phenom.ffwll.local> References: <1366363487-15926-1-git-send-email-daniel.vetter@ffwll.ch> <1366363487-15926-10-git-send-email-daniel.vetter@ffwll.ch> <20130424112319.GL4469@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f176.google.com (mail-ea0-f176.google.com [209.85.215.176]) by gabe.freedesktop.org (Postfix) with ESMTP id D2C35E5D02 for ; Wed, 24 Apr 2013 05:46:36 -0700 (PDT) Received: by mail-ea0-f176.google.com with SMTP id h14so734555eak.21 for ; Wed, 24 Apr 2013 05:46:36 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130424112319.GL4469@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 24, 2013 at 02:23:20PM +0300, Ville Syrj=E4l=E4 wrote: > On Fri, Apr 19, 2013 at 11:24:41AM +0200, Daniel Vetter wrote: > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++-- > > 1 file changed, 18 insertions(+), 2 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index 7cb1abf..b7774c1 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -5766,9 +5766,13 @@ static bool ironlake_get_pipe_config(struct inte= l_crtc *crtc, > > if (!(tmp & PIPECONF_ENABLE)) > > return false; > > = > > - if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) > > + if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { > > pipe_config->has_pch_encoder =3D true; > > = > > + tmp =3D I915_READ(FDI_RX_CTL(crtc->pipe)); > > + pipe_config->fdi_lanes =3D ((tmp >> 19) & 0x3) + 1; > = > Should we add names for the shifts/mask values? Or maybe we have them > already... It's copy&pasta from where we store the lane counts, I can respin the patch and de-magic both places. > And should we check the TX side too and make sure both sides agree on > the number of lanes? Presumably when the RX is enabled, there's a TX for it. And TX state is a bit more messy, especially on haswell. Hence just RX. We could add some checks in the crtc disable code I guess to sanity check TX settings before disabling things (so that we at least notice broken things), but I've figured the black screen would be cause enough for a bug report. So imo ok if we delay adding that until there's a real need for it. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch