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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue
Date: Wed, 24 Apr 2013 20:38:33 +0300	[thread overview]
Message-ID: <20130424173833.GT4469@intel.com> (raw)
In-Reply-To: <1366739541-4565-6-git-send-email-rodrigo.vivi@gmail.com>

On Tue, Apr 23, 2013 at 02:52:20PM -0300, Rodrigo Vivi wrote:
> Display register 420B0h bit 22 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f64f118..cb2d74c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -864,6 +864,13 @@
>  #define   IVB_FBC_RT_BASE_ADDR_SHIFT	12
>  
>  
> +#define _HSW_PIPE_SLICE_CHICKEN_1_A	0x420B0
> +#define _HSW_PIPE_SLICE_CHICKEN_1_B	0x420B4
> +#define   HSW_BYPASS_FBC_QUEUE		(1<<22)
> +#define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
> +					     _HSW_PIPE_SLICE_CHICKEN_1_A, + \
> +					     _HSW_PIPE_SLICE_CHICKEN_1_B)
> +
>  /*
>   * GPIO regs
>   */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 972a1a3..f81b25f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -280,6 +280,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>  		I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
>  		/* WaFbcDisableDpfcClockGating */
>  		I915_WRITE(ILK_DSPCLK_GATE_D, ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
> +	} else {
> +		/* WaFbcAsynchFlipDisableFbcQueue */
> +		I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
> +			   HSW_BYPASS_FBC_QUEUE);
>  	}
>  
>  	I915_WRITE(SNB_DPFC_CTL_SA,
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

  reply	other threads:[~2013-04-24 17:38 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-23 17:52 [PATCH 0/6] Enabling Frame Buffer Compression (FBC) for IVB and HSW Rodrigo Vivi
2013-04-23 17:52 ` [PATCH 1/6] drm/i915: Enable FBC at Ivybridge Rodrigo Vivi
2013-04-23 19:04   ` Matt Turner
2013-04-23 19:57     ` Rodrigo Vivi
2013-04-23 20:55     ` [PATCH] drm/i915: Add support for FBC on Ivybridge Rodrigo Vivi
2013-04-24 16:47       ` Ville Syrjälä
2013-04-25 19:15         ` Rodrigo Vivi
2013-04-23 17:52 ` [PATCH 2/6] drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue Rodrigo Vivi
2013-04-24 17:00   ` Ville Syrjälä
2013-04-23 17:52 ` [PATCH 3/6] drm/i915: IVB FBC WaFbcDisableDpfcClockGating Rodrigo Vivi
2013-04-24 17:15   ` Ville Syrjälä
2013-04-23 17:52 ` [PATCH 4/6] drm/i915: Enable FBC at Haswell Rodrigo Vivi
2013-04-24 17:36   ` Ville Syrjälä
2013-04-23 17:52 ` [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue Rodrigo Vivi
2013-04-24 17:38   ` Ville Syrjälä [this message]
2013-04-23 17:52 ` [PATCH 6/6] drm/i915: HSW FBC WaFbcDisableDpfcClockGating Rodrigo Vivi
2013-04-24 17:41   ` Ville Syrjälä
  -- strict thread matches above, loose matches on Subject: below --
2013-04-25 17:15 [PATCH 1/6] drm/i915: Add support for FBC on Ivybridge Rodrigo Vivi
2013-04-25 17:15 ` [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue Rodrigo Vivi
2013-05-06 22:37 [PATCH 1/6] drm/i915: Add support for FBC on Ivybridge Rodrigo Vivi
2013-05-06 22:37 ` [PATCH 5/6] drm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue Rodrigo Vivi

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