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From: Gleb Natapov <gleb@redhat.com>
To: "Nakajima, Jun" <jun.nakajima@intel.com>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>
Subject: Re: [PATCH 01/12] Subject: [PATCH 01/10] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1
Date: Thu, 25 Apr 2013 11:10:26 +0300	[thread overview]
Message-ID: <20130425081026.GX12401@redhat.com> (raw)
In-Reply-To: <CAL54oT2ej7n9UswusrEdKLh40h7Ewsmz1PZow8U4vfSM_NpyXA@mail.gmail.com>

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On Thu, Apr 25, 2013 at 12:50:19AM -0700, Nakajima, Jun wrote:
> Recent KVM, since http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
> switch the EFER MSR when EPT is used and the host and guest have different
> NX bits. So if we add support for nested EPT (L1 guest using EPT to run L2)
> and want to be able to run recent KVM as L1, we need to allow L1 to use this
> EFER switching feature.
> 
> To do this EFER switching, KVM uses VM_ENTRY/EXIT_LOAD_IA32_EFER if available,
> and if it isn't, it uses the generic VM_ENTRY/EXIT_MSR_LOAD. This patch adds
> support for the former (the latter is still unsupported).
> 
> Nested entry and exit emulation (prepare_vmcs_02 and load_vmcs12_host_state,
> respectively) already handled VM_ENTRY/EXIT_LOAD_IA32_EFER correctly. So all
> that's left to do in this patch is to properly advertise this feature to L1.
> 
> Note that vmcs12's VM_ENTRY/EXIT_LOAD_IA32_EFER are emulated by L0, by using
> vmx_set_efer (which itself sets one of several vmcs02 fields), so we always
> support this feature, regardless of whether the host supports it.
> 
> Signed-off-by: Nadav Har'El <nyh@il.ibm.com>
> Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
> 
> modified:   arch/x86/kvm/vmx.c
> ---
>  arch/x86/kvm/vmx.c | 18 ++++++++++++++----
>  1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 6667042..9e0ec9d 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -2057,6 +2057,7 @@ static __init void nested_vmx_setup_ctls_msrs(void)
>  #else
>   nested_vmx_exit_ctls_high = 0;
>  #endif
> + nested_vmx_exit_ctls_high |= VM_EXIT_LOAD_IA32_EFER;
> 
>   /* entry controls */
>   rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
> @@ -2064,6 +2065,7 @@ static __init void nested_vmx_setup_ctls_msrs(void)
>   nested_vmx_entry_ctls_low = 0;
>   nested_vmx_entry_ctls_high &=
>   VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
> + nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_IA32_EFER;
> 
>   /* cpu-based controls */
>   rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
> @@ -7050,10 +7052,18 @@ static void prepare_vmcs02(struct kvm_vcpu
> *vcpu, struct vmcs12 *vmcs12)
>   vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
>   vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
> 
> - /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
> - vmcs_write32(VM_EXIT_CONTROLS,
> - vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
> - vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
> + /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
> + * we should use its exit controls. Note that IA32_MODE, LOAD_IA32_EFER
> + * bits are further modified by vmx_set_efer() below.
> + */
> + vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
> +
> + /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
> + * emulated by vmx_set_efer(), below.
> + */
> + vmcs_write32(VM_ENTRY_CONTROLS,
> + (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
> + ~VM_ENTRY_IA32E_MODE) |
>   (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
> 
>   if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
> --
> 1.8.2.1.610.g562af5b
> --
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--
			Gleb.

      reply	other threads:[~2013-04-25  8:10 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-25  7:50 [PATCH 01/12] Subject: [PATCH 01/10] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1 Nakajima, Jun
2013-04-25  8:10 ` Gleb Natapov [this message]

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