From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/7] drm/i915: consolidate pch pll computations a bit Date: Thu, 25 Apr 2013 13:58:31 +0300 Message-ID: <20130425105830.GW4469@intel.com> References: <1366362877-15446-1-git-send-email-daniel.vetter@ffwll.ch> <1366362877-15446-2-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A851E5C14 for ; Thu, 25 Apr 2013 03:58:34 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1366362877-15446-2-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Fri, Apr 19, 2013 at 11:14:31AM +0200, Daniel Vetter wrote: > We need the dpll/fp/fp2 values only when we need a pch pll. So move > them together with the code to acquire such a pll. > = > Signed-off-by: Daniel Vetter Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++--------- > 1 file changed, 10 insertions(+), 9 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 3c90605..ca2433b 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5716,7 +5716,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *= crtc, > int plane =3D intel_crtc->plane; > int num_connectors =3D 0; > intel_clock_t clock, reduced_clock; > - u32 dpll, fp =3D 0, fp2 =3D 0; > + u32 dpll =3D 0, fp =3D 0, fp2 =3D 0; > bool ok, has_reduced_clock =3D false; > bool is_lvds =3D false; > struct intel_encoder *encoder; > @@ -5761,14 +5761,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc = *crtc, > if (is_lvds && dev_priv->lvds_dither) > dither =3D true; > = > - fp =3D clock.n << 16 | clock.m1 << 8 | clock.m2; > - if (has_reduced_clock) > - fp2 =3D reduced_clock.n << 16 | reduced_clock.m1 << 8 | > - reduced_clock.m2; > - > - dpll =3D ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock, > - has_reduced_clock ? &fp2 : NULL); > - > DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe)); > drm_mode_debug_printmodeline(mode); > = > @@ -5776,6 +5768,15 @@ static int ironlake_crtc_mode_set(struct drm_crtc = *crtc, > if (intel_crtc->config.has_pch_encoder) { > struct intel_pch_pll *pll; > = > + fp =3D clock.n << 16 | clock.m1 << 8 | clock.m2; > + if (has_reduced_clock) > + fp2 =3D reduced_clock.n << 16 | reduced_clock.m1 << 8 | > + reduced_clock.m2; > + > + dpll =3D ironlake_compute_dpll(intel_crtc, &clock, > + &fp, &reduced_clock, > + has_reduced_clock ? &fp2 : NULL); > + > pll =3D intel_get_pch_pll(intel_crtc, dpll, fp); > if (pll =3D=3D NULL) { > DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", > -- = > 1.7.11.7 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC