From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ua2Mx-0002Lh-PL for qemu-devel@nongnu.org; Wed, 08 May 2013 07:17:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ua2Mt-0002aX-0a for qemu-devel@nongnu.org; Wed, 08 May 2013 07:17:11 -0400 Date: Wed, 8 May 2013 13:16:53 +0200 From: Aurelien Jarno Message-ID: <20130508111652.GM4613@ohm.aurel32.net> References: <1368007612-1873-1-git-send-email-agraf@suse.de> <1368007612-1873-3-git-send-email-agraf@suse.de> <20130508102910.GQ5000@ohm.aurel32.net> <861u9hoj4d.fsf@shell.gmplib.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <861u9hoj4d.fsf@shell.gmplib.org> Subject: Re: [Qemu-devel] [PATCH] PPC: Introduce 32bit only cmp ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Torbjorn Granlund Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Alexander Graf , Richard Henderson On Wed, May 08, 2013 at 12:34:26PM +0200, Torbjorn Granlund wrote: > Aurelien Jarno writes: > > You have to declare the L bit as invalid, so that trying to execute a > 64-bit cmp* instruction on a 32-bit CPU causes an invalid instruction > exception. > > Don't people read what I write? > Quoting the "IBM PowerPC Microprocessor Family: The Programming Environments Manual for 32 and 64-bit Microprocessors": | Note: In 32-bit implementations, if L = 1 the instruction form is invalid. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net