From mboxrd@z Thu Jan  1 00:00:00 1970
From: Gleb Natapov <gleb@redhat.com>
Subject: Re: [nVMX with: v3.9-11789-ge0fd9af] Stack trace when L2 guest is
 rebooted.
Date: Sun, 12 May 2013 18:35:15 +0300
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Cc: Kashyap Chamarthy <kashyap.cv@gmail.com>,
	Jan Kiszka <jan.kiszka@siemens.com>,
	"Nakajima, Jun" <jun.nakajima@intel.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	kvm-owner@vger.kernel.org
To: Abel Gordon <ABELG@il.ibm.com>
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On Sun, May 12, 2013 at 04:48:28PM +0300, Abel Gordon wrote:
> 
> 
> Kashyap Chamarthy <kashyap.cv@gmail.com> wrote on 12/05/2013 04:06:40 PM:
> 
> 
> > > Note shadow vmcs is disabled unless you have a processor
> > > that supports this feature. Do you ?!
> >
> > Yes, I noted this in my previous email. I'm using Intel Haswell.
> >
> > Here's the info from MSR bits on the machine(From `Table 35-3`, MSRs
> > in Procesors Based on Intel Core Microarchitecture, `Volume 3C of the
> > SDM )
> > --------------------------------------------
> >     # Read msr value
> >     $ rdmsr 0x48B
> >     7cff00000000
> >
> >     # Check Shadow VMCS is enabled:
> >     $ rdmsr 0x00000485
> >     300481e5
> > --------------------------------------------
> >
> > And, on the Kernel command line:
> > --------------------------------------------
> >     # nested
> >     $ cat /sys/module/kvm_intel/parameters/nested
> >     Y
> >
> >     # shadow VMCS
> >     $ cat /sys/module/kvm_intel/parameters/enable_shadow_vmcs
> >     Y
> > --------------------------------------------
> 
> Yep, shadow-vmcs enabled :)
> 
> 
> > Just for reference, here's the detailed procedure I noted  while
> > testing it on Haswell --
> > https://raw.github.com/kashyapc/nvmx-haswell/master/SETUP-nVMX.rst
> >
> > Also note you can disable
> > > shadow-vmcs using the kvm-intel kernel module parameter
> > > "enable_shadow_vmcs".
> >
> > Yes, to test w/o shadow VMCS, I disabled it by adding "options
> > kvm-intel enable_shadow_vmcs=y" to /etc/modprobe.d/dist.conf & reboot
> > the host.
> 
> I assume you meant enable_shadow_vmcs=n :)
> 
> Small question: did you try to disable apicv/posted interrupts at L0 ?
> (for L1 you can't enable these features because they are not emulated)
> 
AFAIK Haswell does not have apicv/posted interrupts. Not the one I have
access to anyway.

--
			Gleb.