diff for duplicates of <20130513192513.10068.7049@quantum> diff --git a/a/1.txt b/N1/1.txt index 54ddef1..ea72598 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,9 @@ Quoting Yuantian.Tang@freescale.com (2013-04-09 01:46:26) > From: Tang Yuantian <yuantian.tang@freescale.com> -> = - +> > This adds the clock driver for Freescale PowerPC corenet > series SoCs using common clock infrastructure. -> = - +> > Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> > Signed-off-by: Li Yang <leoli@freescale.com> @@ -23,19 +21,15 @@ Mike > - remove the module author and description > v2: > - add the document for device tree clock bindings -> = - +> > arch/powerpc/platforms/Kconfig.cputype | 1 + > drivers/clk/Kconfig | 7 + > drivers/clk/Makefile | 1 + -> drivers/clk/clk-ppc-corenet.c | 280 +++++++++++++++++++++++++++= -++++++ +> drivers/clk/clk-ppc-corenet.c | 280 +++++++++++++++++++++++++++++++++ > 4 files changed, 289 insertions(+) > create mode 100644 drivers/clk/clk-ppc-corenet.c -> = - -> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platfo= -rms/Kconfig.cputype +> +> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype > index 18e3b76..cf065b8 100644 > --- a/arch/powerpc/platforms/Kconfig.cputype > +++ b/arch/powerpc/platforms/Kconfig.cputype @@ -52,11 +46,9 @@ rms/Kconfig.cputype > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -63,6 +63,13 @@ config CLK_TWL6040 -> McPDM. McPDM module is using the external bit clock on the McPD= -M bus +> McPDM. McPDM module is using the external bit clock on the McPDM bus > as functional clock. -> = - +> > +config CLK_PPC_CORENET > + bool "Clock driver for PowerPC corenet platforms" > + depends on PPC_E500MC && OF @@ -65,18 +57,17 @@ M bus > + platforms using common clock framework. > + > endmenu -> = - +> > source "drivers/clk/mvebu/Kconfig" > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index 300d477..6720319 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile -> @@ -34,3 +34,4 @@ obj-$(CONFIG_X86) +=3D x86/ -> obj-$(CONFIG_COMMON_CLK_WM831X) +=3D clk-wm831x.o -> obj-$(CONFIG_COMMON_CLK_MAX77686) +=3D clk-max77686.o -> obj-$(CONFIG_CLK_TWL6040) +=3D clk-twl6040.o -> +obj-$(CONFIG_CLK_PPC_CORENET) +=3D clk-ppc-corenet.o +> @@ -34,3 +34,4 @@ obj-$(CONFIG_X86) += x86/ +> obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o +> obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o +> obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o +> +obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o > diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c > new file mode 100644 > index 0000000..a2d483f @@ -116,13 +107,13 @@ M bus > + > +static int cmux_set_parent(struct clk_hw *hw, u8 idx) > +{ -> + struct cmux_clk *clk =3D to_cmux_clk(hw); +> + struct cmux_clk *clk = to_cmux_clk(hw); > + u32 clksel; > + -> + clksel =3D ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll; +> + clksel = ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll; > + if (clk->flags & CLKSEL_ADJUST) -> + clksel +=3D 8; -> + clksel =3D (clksel & 0xf) << CLKSEL_SHIFT; +> + clksel += 8; +> + clksel = (clksel & 0xf) << CLKSEL_SHIFT; > + iowrite32be(clksel, clk->reg); > + > + return 0; @@ -130,21 +121,21 @@ M bus > + > +static u8 cmux_get_parent(struct clk_hw *hw) > +{ -> + struct cmux_clk *clk =3D to_cmux_clk(hw); +> + struct cmux_clk *clk = to_cmux_clk(hw); > + u32 clksel; > + -> + clksel =3D ioread32be(clk->reg); -> + clksel =3D (clksel >> CLKSEL_SHIFT) & 0xf; +> + clksel = ioread32be(clk->reg); +> + clksel = (clksel >> CLKSEL_SHIFT) & 0xf; > + if (clk->flags & CLKSEL_ADJUST) -> + clksel -=3D 8; -> + clksel =3D (clksel >> 2) * clocks_per_pll + clksel % 4; +> + clksel -= 8; +> + clksel = (clksel >> 2) * clocks_per_pll + clksel % 4; > + > + return clksel; > +} > + -> +const struct clk_ops cmux_ops =3D { -> + .get_parent =3D cmux_get_parent, -> + .set_parent =3D cmux_set_parent, +> +const struct clk_ops cmux_ops = { +> + .get_parent = cmux_get_parent, +> + .set_parent = cmux_set_parent, > +}; > + > +static void __init core_mux_init(struct device_node *np) @@ -158,60 +149,59 @@ M bus > + const char *clk_name; > + const char **parent_names; > + -> + rc =3D of_property_read_u32(np, "reg", &offset); +> + rc = of_property_read_u32(np, "reg", &offset); > + if (rc) { > + pr_err("%s: could not get reg property\n", np->name); > + return; > + } > + > + /* get the input clock source count */ -> + count =3D of_property_count_strings(np, "clock-names"); +> + count = of_property_count_strings(np, "clock-names"); > + if (count < 0) { > + pr_err("%s: get clock count error\n", np->name); > + return; > + } -> + parent_names =3D kzalloc((sizeof(char *) * count), GFP_KERNEL); +> + parent_names = kzalloc((sizeof(char *) * count), GFP_KERNEL); > + if (!parent_names) { > + pr_err("%s: could not allocate parent_names\n", __func__); > + return; > + } > + -> + for (i =3D 0; i < count; i++) -> + parent_names[i] =3D of_clk_get_parent_name(np, i); +> + for (i = 0; i < count; i++) +> + parent_names[i] = of_clk_get_parent_name(np, i); > + -> + cmux_clk =3D kzalloc(sizeof(struct cmux_clk), GFP_KERNEL); +> + cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL); > + if (!cmux_clk) { > + pr_err("%s: could not allocate cmux_clk\n", __func__); > + goto err_name; > + } -> + cmux_clk->reg =3D base + offset; +> + cmux_clk->reg = base + offset; > + -> + node =3D of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen"= -); -> + if (node && (offset >=3D 0x80)) -> + cmux_clk->flags =3D CLKSEL_ADJUST; +> + node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen"); +> + if (node && (offset >= 0x80)) +> + cmux_clk->flags = CLKSEL_ADJUST; > + -> + rc =3D of_property_read_string_index(np, "clock-output-names", +> + rc = of_property_read_string_index(np, "clock-output-names", > + 0, &clk_name); > + if (rc) { > + pr_err("%s: read clock names error\n", np->name); > + goto err_clk; > + } > + -> + init.name =3D clk_name; -> + init.ops =3D &cmux_ops; -> + init.parent_names =3D parent_names; -> + init.num_parents =3D count; -> + init.flags =3D 0; -> + cmux_clk->hw.init =3D &init; +> + init.name = clk_name; +> + init.ops = &cmux_ops; +> + init.parent_names = parent_names; +> + init.num_parents = count; +> + init.flags = 0; +> + cmux_clk->hw.init = &init; > + -> + clk =3D clk_register(NULL, &cmux_clk->hw); +> + clk = clk_register(NULL, &cmux_clk->hw); > + if (IS_ERR(clk)) { > + pr_err("%s: could not register clock\n", clk_name); > + goto err_clk; > + } > + -> + rc =3D of_clk_add_provider(np, of_clk_src_simple_get, clk); +> + rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); > + if (rc) { > + pr_err("Could not register clock provider for node:%s\n", > + np->name); @@ -234,88 +224,81 @@ M bus > + struct clk_onecell_data *onecell_data; > + struct clk **subclks; > + -> + rc =3D of_property_read_u32(np, "reg", &offset); +> + rc = of_property_read_u32(np, "reg", &offset); > + if (rc) { > + pr_err("%s: could not get reg property\n", np->name); > + return; > + } > + > + /* get the multiple of PLL */ -> + mult =3D ioread32be(base + offset); +> + mult = ioread32be(base + offset); > + > + /* check if this PLL is disabled */ > + if (mult & PLL_KILL) { > + pr_debug("PLL:%s is disabled\n", np->name); > + return; > + } -> + mult =3D (mult >> 1) & 0x3f; +> + mult = (mult >> 1) & 0x3f; > + -> + parent_name =3D of_clk_get_parent_name(np, 0); +> + parent_name = of_clk_get_parent_name(np, 0); > + if (!parent_name) { > + pr_err("PLL: %s must have a parent\n", np->name); > + return; > + } > + -> + count =3D of_property_count_strings(np, "clock-output-names"); +> + count = of_property_count_strings(np, "clock-output-names"); > + if (count < 0 || count > 4) { > + pr_err("%s: clock is not supported\n", np->name); > + return; > + } > + > + /* output clock number per PLL */ -> + clocks_per_pll =3D count; +> + clocks_per_pll = count; > + -> + subclks =3D kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); +> + subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); > + if (!subclks) { > + pr_err("%s: could not allocate subclks\n", __func__); > + return; > + } > + -> + onecell_data =3D kzalloc(sizeof(struct clk_onecell_data), GFP_KER= -NEL); +> + onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); > + if (!onecell_data) { > + pr_err("%s: could not allocate onecell_data\n", __func__); > + goto err_clks; > + } > + -> + for (i =3D 0; i < count; i++) { -> + rc =3D of_property_read_string_index(np, "clock-output-na= -mes", +> + for (i = 0; i < count; i++) { +> + rc = of_property_read_string_index(np, "clock-output-names", > + i, &clk_name); > + if (rc) { -> + pr_err("%s: could not get clock names\n", np->nam= -e); +> + pr_err("%s: could not get clock names\n", np->name); > + goto err_cell; > + } > + > + /* -> + * when count =3D=3D 4, there are 4 output clocks: +> + * when count == 4, there are 4 output clocks: > + * /1, /2, /3, /4 respectively > + * when count < 4, there are at least 2 output clocks: -> + * /1, /2, (/4, if count =3D=3D 3) respectively. +> + * /1, /2, (/4, if count == 3) respectively. > + */ -> + if (count =3D=3D 4) -> + subclks[i] =3D clk_register_fixed_factor(NULL, cl= -k_name, +> + if (count == 4) +> + subclks[i] = clk_register_fixed_factor(NULL, clk_name, > + parent_name, 0, mult, 1 + i); > + else > + -> + subclks[i] =3D clk_register_fixed_factor(NULL, cl= -k_name, +> + subclks[i] = clk_register_fixed_factor(NULL, clk_name, > + parent_name, 0, mult, 1 << i); > + > + if (IS_ERR(subclks[i])) { -> + pr_err("%s: could not register clock\n", clk_name= -); +> + pr_err("%s: could not register clock\n", clk_name); > + goto err_cell; > + } > + } > + -> + onecell_data->clks =3D subclks; -> + onecell_data->clk_num =3D count; +> + onecell_data->clks = subclks; +> + onecell_data->clk_num = count; > + -> + rc =3D of_clk_add_provider(np, of_clk_src_onecell_get, onecell_da= -ta); +> + rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data); > + if (rc) { > + pr_err("Could not register clk provider for node:%s\n", > + np->name); @@ -329,12 +312,10 @@ ta); > + kfree(subclks); > +} > + -> +static const struct of_device_id clk_match[] __initconst =3D { -> + { .compatible =3D "fixed-clock", .data =3D of_fixed_clk_setup, }, -> + { .compatible =3D "fsl,core-pll-clock", .data =3D core_pll_init, = -}, -> + { .compatible =3D "fsl,core-mux-clock", .data =3D core_mux_init, = -}, +> +static const struct of_device_id clk_match[] __initconst = { +> + { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, +> + { .compatible = "fsl,core-pll-clock", .data = core_pll_init, }, +> + { .compatible = "fsl,core-mux-clock", .data = core_mux_init, }, > + {} > +}; > + @@ -342,8 +323,8 @@ ta); > +{ > + struct device_node *np; > + -> + np =3D pdev->dev.of_node; -> + base =3D of_iomap(np, 0); +> + np = pdev->dev.of_node; +> + base = of_iomap(np, 0); > + if (!base) { > + dev_err(&pdev->dev, "iomap error\n"); > + return -ENOMEM; @@ -353,19 +334,19 @@ ta); > + return 0; > +} > + -> +static const struct of_device_id ppc_clk_ids[] __initconst =3D { -> + { .compatible =3D "fsl,qoriq-clockgen-1.0", }, -> + { .compatible =3D "fsl,qoriq-clockgen-2", }, +> +static const struct of_device_id ppc_clk_ids[] __initconst = { +> + { .compatible = "fsl,qoriq-clockgen-1.0", }, +> + { .compatible = "fsl,qoriq-clockgen-2", }, > + {} > +}; > + -> +static struct platform_driver ppc_corenet_clk_driver =3D { -> + .driver =3D { -> + .name =3D "ppc_corenet_clock", -> + .owner =3D THIS_MODULE, -> + .of_match_table =3D ppc_clk_ids, +> +static struct platform_driver ppc_corenet_clk_driver = { +> + .driver = { +> + .name = "ppc_corenet_clock", +> + .owner = THIS_MODULE, +> + .of_match_table = ppc_clk_ids, > + }, -> + .probe =3D ppc_corenet_clk_probe, +> + .probe = ppc_corenet_clk_probe, > +}; > + > +static int __init ppc_corenet_clk_init(void) @@ -373,6 +354,5 @@ ta); > + return platform_driver_register(&ppc_corenet_clk_driver); > +} > +subsys_initcall(ppc_corenet_clk_init); -> -- = - +> -- > 1.8.0 diff --git a/a/content_digest b/N1/content_digest index cf7f46a..169d7bb 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,8 +2,6 @@ "From\0Mike Turquette <mturquette@linaro.org>\0" "Subject\0Re: [PATCH v3] clk: add PowerPC corenet clock driver support\0" "Date\0Mon, 13 May 2013 12:25:13 -0700\0" - "To\0<Yuantian.Tang@freescale.com>" - "\0" "Cc\0ulf.hansson@linaro.org" linux-doc@vger.kernel.org viresh.kumar@linaro.org @@ -17,12 +15,10 @@ "b\0" "Quoting Yuantian.Tang@freescale.com (2013-04-09 01:46:26)\n" "> From: Tang Yuantian <yuantian.tang@freescale.com>\n" - "> =\n" - "\n" + "> \n" "> This adds the clock driver for Freescale PowerPC corenet\n" "> series SoCs using common clock infrastructure.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>\n" "> Signed-off-by: Li Yang <leoli@freescale.com>\n" "\n" @@ -40,19 +36,15 @@ "> - remove the module author and description\n" "> v2:\n" "> - add the document for device tree clock bindings\n" - "> =\n" - "\n" + "> \n" "> arch/powerpc/platforms/Kconfig.cputype | 1 +\n" "> drivers/clk/Kconfig | 7 +\n" "> drivers/clk/Makefile | 1 +\n" - "> drivers/clk/clk-ppc-corenet.c | 280 +++++++++++++++++++++++++++=\n" - "++++++\n" + "> drivers/clk/clk-ppc-corenet.c | 280 +++++++++++++++++++++++++++++++++\n" "> 4 files changed, 289 insertions(+)\n" "> create mode 100644 drivers/clk/clk-ppc-corenet.c\n" - "> =\n" - "\n" - "> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platfo=\n" - "rms/Kconfig.cputype\n" + "> \n" + "> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype\n" "> index 18e3b76..cf065b8 100644\n" "> --- a/arch/powerpc/platforms/Kconfig.cputype\n" "> +++ b/arch/powerpc/platforms/Kconfig.cputype\n" @@ -69,11 +61,9 @@ "> --- a/drivers/clk/Kconfig\n" "> +++ b/drivers/clk/Kconfig\n" "> @@ -63,6 +63,13 @@ config CLK_TWL6040\n" - "> McPDM. McPDM module is using the external bit clock on the McPD=\n" - "M bus\n" + "> McPDM. McPDM module is using the external bit clock on the McPDM bus\n" "> as functional clock.\n" - "> =\n" - "\n" + "> \n" "> +config CLK_PPC_CORENET\n" "> + bool \"Clock driver for PowerPC corenet platforms\"\n" "> + depends on PPC_E500MC && OF\n" @@ -82,18 +72,17 @@ "> + platforms using common clock framework.\n" "> +\n" "> endmenu\n" - "> =\n" - "\n" + "> \n" "> source \"drivers/clk/mvebu/Kconfig\"\n" "> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\n" "> index 300d477..6720319 100644\n" "> --- a/drivers/clk/Makefile\n" "> +++ b/drivers/clk/Makefile\n" - "> @@ -34,3 +34,4 @@ obj-$(CONFIG_X86) +=3D x86/\n" - "> obj-$(CONFIG_COMMON_CLK_WM831X) +=3D clk-wm831x.o\n" - "> obj-$(CONFIG_COMMON_CLK_MAX77686) +=3D clk-max77686.o\n" - "> obj-$(CONFIG_CLK_TWL6040) +=3D clk-twl6040.o\n" - "> +obj-$(CONFIG_CLK_PPC_CORENET) +=3D clk-ppc-corenet.o\n" + "> @@ -34,3 +34,4 @@ obj-$(CONFIG_X86) += x86/\n" + "> obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o\n" + "> obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o\n" + "> obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o\n" + "> +obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o\n" "> diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c\n" "> new file mode 100644\n" "> index 0000000..a2d483f\n" @@ -133,13 +122,13 @@ "> +\n" "> +static int cmux_set_parent(struct clk_hw *hw, u8 idx)\n" "> +{\n" - "> + struct cmux_clk *clk =3D to_cmux_clk(hw);\n" + "> + struct cmux_clk *clk = to_cmux_clk(hw);\n" "> + u32 clksel;\n" "> +\n" - "> + clksel =3D ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll;\n" + "> + clksel = ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll;\n" "> + if (clk->flags & CLKSEL_ADJUST)\n" - "> + clksel +=3D 8;\n" - "> + clksel =3D (clksel & 0xf) << CLKSEL_SHIFT;\n" + "> + clksel += 8;\n" + "> + clksel = (clksel & 0xf) << CLKSEL_SHIFT;\n" "> + iowrite32be(clksel, clk->reg);\n" "> +\n" "> + return 0;\n" @@ -147,21 +136,21 @@ "> +\n" "> +static u8 cmux_get_parent(struct clk_hw *hw)\n" "> +{\n" - "> + struct cmux_clk *clk =3D to_cmux_clk(hw);\n" + "> + struct cmux_clk *clk = to_cmux_clk(hw);\n" "> + u32 clksel;\n" "> +\n" - "> + clksel =3D ioread32be(clk->reg);\n" - "> + clksel =3D (clksel >> CLKSEL_SHIFT) & 0xf;\n" + "> + clksel = ioread32be(clk->reg);\n" + "> + clksel = (clksel >> CLKSEL_SHIFT) & 0xf;\n" "> + if (clk->flags & CLKSEL_ADJUST)\n" - "> + clksel -=3D 8;\n" - "> + clksel =3D (clksel >> 2) * clocks_per_pll + clksel % 4;\n" + "> + clksel -= 8;\n" + "> + clksel = (clksel >> 2) * clocks_per_pll + clksel % 4;\n" "> +\n" "> + return clksel;\n" "> +}\n" "> +\n" - "> +const struct clk_ops cmux_ops =3D {\n" - "> + .get_parent =3D cmux_get_parent,\n" - "> + .set_parent =3D cmux_set_parent,\n" + "> +const struct clk_ops cmux_ops = {\n" + "> + .get_parent = cmux_get_parent,\n" + "> + .set_parent = cmux_set_parent,\n" "> +};\n" "> +\n" "> +static void __init core_mux_init(struct device_node *np)\n" @@ -175,60 +164,59 @@ "> + const char *clk_name;\n" "> + const char **parent_names;\n" "> +\n" - "> + rc =3D of_property_read_u32(np, \"reg\", &offset);\n" + "> + rc = of_property_read_u32(np, \"reg\", &offset);\n" "> + if (rc) {\n" "> + pr_err(\"%s: could not get reg property\\n\", np->name);\n" "> + return;\n" "> + }\n" "> +\n" "> + /* get the input clock source count */\n" - "> + count =3D of_property_count_strings(np, \"clock-names\");\n" + "> + count = of_property_count_strings(np, \"clock-names\");\n" "> + if (count < 0) {\n" "> + pr_err(\"%s: get clock count error\\n\", np->name);\n" "> + return;\n" "> + }\n" - "> + parent_names =3D kzalloc((sizeof(char *) * count), GFP_KERNEL);\n" + "> + parent_names = kzalloc((sizeof(char *) * count), GFP_KERNEL);\n" "> + if (!parent_names) {\n" "> + pr_err(\"%s: could not allocate parent_names\\n\", __func__);\n" "> + return;\n" "> + }\n" "> +\n" - "> + for (i =3D 0; i < count; i++)\n" - "> + parent_names[i] =3D of_clk_get_parent_name(np, i);\n" + "> + for (i = 0; i < count; i++)\n" + "> + parent_names[i] = of_clk_get_parent_name(np, i);\n" "> +\n" - "> + cmux_clk =3D kzalloc(sizeof(struct cmux_clk), GFP_KERNEL);\n" + "> + cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL);\n" "> + if (!cmux_clk) {\n" "> + pr_err(\"%s: could not allocate cmux_clk\\n\", __func__);\n" "> + goto err_name;\n" "> + }\n" - "> + cmux_clk->reg =3D base + offset;\n" + "> + cmux_clk->reg = base + offset;\n" "> +\n" - "> + node =3D of_find_compatible_node(NULL, NULL, \"fsl,p4080-clockgen\"=\n" - ");\n" - "> + if (node && (offset >=3D 0x80))\n" - "> + cmux_clk->flags =3D CLKSEL_ADJUST;\n" + "> + node = of_find_compatible_node(NULL, NULL, \"fsl,p4080-clockgen\");\n" + "> + if (node && (offset >= 0x80))\n" + "> + cmux_clk->flags = CLKSEL_ADJUST;\n" "> +\n" - "> + rc =3D of_property_read_string_index(np, \"clock-output-names\",\n" + "> + rc = of_property_read_string_index(np, \"clock-output-names\",\n" "> + 0, &clk_name);\n" "> + if (rc) {\n" "> + pr_err(\"%s: read clock names error\\n\", np->name);\n" "> + goto err_clk;\n" "> + }\n" "> +\n" - "> + init.name =3D clk_name;\n" - "> + init.ops =3D &cmux_ops;\n" - "> + init.parent_names =3D parent_names;\n" - "> + init.num_parents =3D count;\n" - "> + init.flags =3D 0;\n" - "> + cmux_clk->hw.init =3D &init;\n" + "> + init.name = clk_name;\n" + "> + init.ops = &cmux_ops;\n" + "> + init.parent_names = parent_names;\n" + "> + init.num_parents = count;\n" + "> + init.flags = 0;\n" + "> + cmux_clk->hw.init = &init;\n" "> +\n" - "> + clk =3D clk_register(NULL, &cmux_clk->hw);\n" + "> + clk = clk_register(NULL, &cmux_clk->hw);\n" "> + if (IS_ERR(clk)) {\n" "> + pr_err(\"%s: could not register clock\\n\", clk_name);\n" "> + goto err_clk;\n" "> + }\n" "> +\n" - "> + rc =3D of_clk_add_provider(np, of_clk_src_simple_get, clk);\n" + "> + rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);\n" "> + if (rc) {\n" "> + pr_err(\"Could not register clock provider for node:%s\\n\",\n" "> + np->name);\n" @@ -251,88 +239,81 @@ "> + struct clk_onecell_data *onecell_data;\n" "> + struct clk **subclks;\n" "> +\n" - "> + rc =3D of_property_read_u32(np, \"reg\", &offset);\n" + "> + rc = of_property_read_u32(np, \"reg\", &offset);\n" "> + if (rc) {\n" "> + pr_err(\"%s: could not get reg property\\n\", np->name);\n" "> + return;\n" "> + }\n" "> +\n" "> + /* get the multiple of PLL */\n" - "> + mult =3D ioread32be(base + offset);\n" + "> + mult = ioread32be(base + offset);\n" "> +\n" "> + /* check if this PLL is disabled */\n" "> + if (mult & PLL_KILL) {\n" "> + pr_debug(\"PLL:%s is disabled\\n\", np->name);\n" "> + return;\n" "> + }\n" - "> + mult =3D (mult >> 1) & 0x3f;\n" + "> + mult = (mult >> 1) & 0x3f;\n" "> +\n" - "> + parent_name =3D of_clk_get_parent_name(np, 0);\n" + "> + parent_name = of_clk_get_parent_name(np, 0);\n" "> + if (!parent_name) {\n" "> + pr_err(\"PLL: %s must have a parent\\n\", np->name);\n" "> + return;\n" "> + }\n" "> +\n" - "> + count =3D of_property_count_strings(np, \"clock-output-names\");\n" + "> + count = of_property_count_strings(np, \"clock-output-names\");\n" "> + if (count < 0 || count > 4) {\n" "> + pr_err(\"%s: clock is not supported\\n\", np->name);\n" "> + return;\n" "> + }\n" "> +\n" "> + /* output clock number per PLL */\n" - "> + clocks_per_pll =3D count;\n" + "> + clocks_per_pll = count;\n" "> +\n" - "> + subclks =3D kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);\n" + "> + subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);\n" "> + if (!subclks) {\n" "> + pr_err(\"%s: could not allocate subclks\\n\", __func__);\n" "> + return;\n" "> + }\n" "> +\n" - "> + onecell_data =3D kzalloc(sizeof(struct clk_onecell_data), GFP_KER=\n" - "NEL);\n" + "> + onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);\n" "> + if (!onecell_data) {\n" "> + pr_err(\"%s: could not allocate onecell_data\\n\", __func__);\n" "> + goto err_clks;\n" "> + }\n" "> +\n" - "> + for (i =3D 0; i < count; i++) {\n" - "> + rc =3D of_property_read_string_index(np, \"clock-output-na=\n" - "mes\",\n" + "> + for (i = 0; i < count; i++) {\n" + "> + rc = of_property_read_string_index(np, \"clock-output-names\",\n" "> + i, &clk_name);\n" "> + if (rc) {\n" - "> + pr_err(\"%s: could not get clock names\\n\", np->nam=\n" - "e);\n" + "> + pr_err(\"%s: could not get clock names\\n\", np->name);\n" "> + goto err_cell;\n" "> + }\n" "> +\n" "> + /*\n" - "> + * when count =3D=3D 4, there are 4 output clocks:\n" + "> + * when count == 4, there are 4 output clocks:\n" "> + * /1, /2, /3, /4 respectively\n" "> + * when count < 4, there are at least 2 output clocks:\n" - "> + * /1, /2, (/4, if count =3D=3D 3) respectively.\n" + "> + * /1, /2, (/4, if count == 3) respectively.\n" "> + */\n" - "> + if (count =3D=3D 4)\n" - "> + subclks[i] =3D clk_register_fixed_factor(NULL, cl=\n" - "k_name,\n" + "> + if (count == 4)\n" + "> + subclks[i] = clk_register_fixed_factor(NULL, clk_name,\n" "> + parent_name, 0, mult, 1 + i);\n" "> + else\n" "> +\n" - "> + subclks[i] =3D clk_register_fixed_factor(NULL, cl=\n" - "k_name,\n" + "> + subclks[i] = clk_register_fixed_factor(NULL, clk_name,\n" "> + parent_name, 0, mult, 1 << i);\n" "> +\n" "> + if (IS_ERR(subclks[i])) {\n" - "> + pr_err(\"%s: could not register clock\\n\", clk_name=\n" - ");\n" + "> + pr_err(\"%s: could not register clock\\n\", clk_name);\n" "> + goto err_cell;\n" "> + }\n" "> + }\n" "> +\n" - "> + onecell_data->clks =3D subclks;\n" - "> + onecell_data->clk_num =3D count;\n" + "> + onecell_data->clks = subclks;\n" + "> + onecell_data->clk_num = count;\n" "> +\n" - "> + rc =3D of_clk_add_provider(np, of_clk_src_onecell_get, onecell_da=\n" - "ta);\n" + "> + rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);\n" "> + if (rc) {\n" "> + pr_err(\"Could not register clk provider for node:%s\\n\",\n" "> + np->name);\n" @@ -346,12 +327,10 @@ "> + kfree(subclks);\n" "> +}\n" "> +\n" - "> +static const struct of_device_id clk_match[] __initconst =3D {\n" - "> + { .compatible =3D \"fixed-clock\", .data =3D of_fixed_clk_setup, },\n" - "> + { .compatible =3D \"fsl,core-pll-clock\", .data =3D core_pll_init, =\n" - "},\n" - "> + { .compatible =3D \"fsl,core-mux-clock\", .data =3D core_mux_init, =\n" - "},\n" + "> +static const struct of_device_id clk_match[] __initconst = {\n" + "> + { .compatible = \"fixed-clock\", .data = of_fixed_clk_setup, },\n" + "> + { .compatible = \"fsl,core-pll-clock\", .data = core_pll_init, },\n" + "> + { .compatible = \"fsl,core-mux-clock\", .data = core_mux_init, },\n" "> + {}\n" "> +};\n" "> +\n" @@ -359,8 +338,8 @@ "> +{\n" "> + struct device_node *np;\n" "> +\n" - "> + np =3D pdev->dev.of_node;\n" - "> + base =3D of_iomap(np, 0);\n" + "> + np = pdev->dev.of_node;\n" + "> + base = of_iomap(np, 0);\n" "> + if (!base) {\n" "> + dev_err(&pdev->dev, \"iomap error\\n\");\n" "> + return -ENOMEM;\n" @@ -370,19 +349,19 @@ "> + return 0;\n" "> +}\n" "> +\n" - "> +static const struct of_device_id ppc_clk_ids[] __initconst =3D {\n" - "> + { .compatible =3D \"fsl,qoriq-clockgen-1.0\", },\n" - "> + { .compatible =3D \"fsl,qoriq-clockgen-2\", },\n" + "> +static const struct of_device_id ppc_clk_ids[] __initconst = {\n" + "> + { .compatible = \"fsl,qoriq-clockgen-1.0\", },\n" + "> + { .compatible = \"fsl,qoriq-clockgen-2\", },\n" "> + {}\n" "> +};\n" "> +\n" - "> +static struct platform_driver ppc_corenet_clk_driver =3D {\n" - "> + .driver =3D {\n" - "> + .name =3D \"ppc_corenet_clock\",\n" - "> + .owner =3D THIS_MODULE,\n" - "> + .of_match_table =3D ppc_clk_ids,\n" + "> +static struct platform_driver ppc_corenet_clk_driver = {\n" + "> + .driver = {\n" + "> + .name = \"ppc_corenet_clock\",\n" + "> + .owner = THIS_MODULE,\n" + "> + .of_match_table = ppc_clk_ids,\n" "> + },\n" - "> + .probe =3D ppc_corenet_clk_probe,\n" + "> + .probe = ppc_corenet_clk_probe,\n" "> +};\n" "> +\n" "> +static int __init ppc_corenet_clk_init(void)\n" @@ -390,8 +369,7 @@ "> + return platform_driver_register(&ppc_corenet_clk_driver);\n" "> +}\n" "> +subsys_initcall(ppc_corenet_clk_init);\n" - "> -- =\n" - "\n" + "> -- \n" > 1.8.0 -2de127c29eb34c236bef14f587d45ff503a5742ae456938939e82bbc9db5bd42 +80ee34ea16228946e6a69ad0efa945cd55b2032d4bdcade2a34157a0a633ddaf
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