From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40116) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UdOf1-0004vp-AP for qemu-devel@nongnu.org; Fri, 17 May 2013 13:41:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UdOf0-0005Iz-4n for qemu-devel@nongnu.org; Fri, 17 May 2013 13:41:43 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:53307) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UdOez-0005Il-Qr for qemu-devel@nongnu.org; Fri, 17 May 2013 13:41:42 -0400 Date: Fri, 17 May 2013 19:41:33 +0200 From: Aurelien Jarno Message-ID: <20130517174133.GC5002@ohm.aurel32.net> References: <1368408937-114555-1-git-send-email-petar.jovanovic@rt-rk.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1368408937-114555-1-git-send-email-petar.jovanovic@rt-rk.com> Subject: Re: [Qemu-devel] [PATCH v2] target-mips: clean-up in BIT_INSV List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Petar Jovanovic Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, petar.jovanovic@imgtec.com On Mon, May 13, 2013 at 03:35:37AM +0200, Petar Jovanovic wrote: > From: Petar Jovanovic > > This is a small follow-up change to "fix incorrect behaviour for INSV". > > It includes two minor modifications: > > - sizefilter is constant so it can be moved inside of the block, > - several lines of the code are replaced with a call to deposit64. > > No functional change. > > Signed-off-by: Petar Jovanovic > --- > v2: > > - version one was based on Aurelien comments, > - version two includes update (use of deposit64 helper) per Peter > Maydell's suggestion. > > target-mips/dsp_helper.c | 17 +++++++---------- > 1 file changed, 7 insertions(+), 10 deletions(-) This version is indeed better. I have applied it in my queue for after 1.6, replacing the previous version. Thanks. > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c > index 9212789..af2aa05 100644 > --- a/target-mips/dsp_helper.c > +++ b/target-mips/dsp_helper.c > @@ -19,6 +19,7 @@ > > #include "cpu.h" > #include "helper.h" > +#include "qemu/bitops.h" > > /* As the byte ordering doesn't matter, i.e. all columns are treated > identically, these unions can be used directly. */ > @@ -2900,13 +2901,13 @@ target_ulong helper_bitrev(target_ulong rt) > return (target_ulong)rd; > } > > -#define BIT_INSV(name, posfilter, sizefilter, ret_type) \ > +#define BIT_INSV(name, posfilter, ret_type) \ > target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \ > target_ulong rt) \ > { \ > uint32_t pos, size, msb, lsb; \ > - target_ulong filter; \ > - target_ulong temp, temprs, temprt; \ > + uint32_t const sizefilter = 0x3F; \ > + target_ulong temp; \ > target_ulong dspc; \ > \ > dspc = env->active_tc.DSPControl; \ > @@ -2921,18 +2922,14 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \ > return rt; \ > } \ > \ > - filter = ((int64_t)0x01 << size) - 1; \ > - filter = filter << pos; \ > - temprs = (rs << pos) & filter; \ > - temprt = rt & ~filter; \ > - temp = temprs | temprt; \ > + temp = deposit64(rt, pos, size, rs); \ > \ > return (target_long)(ret_type)temp; \ > } > > -BIT_INSV(insv, 0x1F, 0x3F, int32_t); > +BIT_INSV(insv, 0x1F, int32_t); > #ifdef TARGET_MIPS64 > -BIT_INSV(dinsv, 0x7F, 0x3F, target_long); > +BIT_INSV(dinsv, 0x7F, target_long); > #endif > > #undef BIT_INSV > -- > 1.7.9.5 > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net