Re: [PATCH 8/9] drm/i915: MCH_SSKPD is a 64 bit register on Haswell

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Fri, May 03, 2013 at 05:23:44PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
> have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
> the new one is not zero.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 59bac2e..b56de92 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4491,7 +4491,7 @@ void intel_init_pm(struct drm_device *dev)
>  			}
>  			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
>  		} else if (IS_HASWELL(dev)) {
> -			if (SNB_READ_WM0_LATENCY()) {
> +			if (I915_READ64(MCH_SSKPD)) {
>  				dev_priv->display.update_wm = haswell_update_wm;
>  				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
>  			} else {
> -- 
> 1.7.10.4
> 
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-- 
Ville Syrjälä
Intel OTC