From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2 1/3] drm/i915: Disable primary plane trickle feed for g4x Date: Tue, 21 May 2013 15:35:06 +0300 Message-ID: <20130521123506.GA16772@intel.com> References: <1369139314-3003-1-git-send-email-ville.syrjala@linux.intel.com> <1369139314-3003-2-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 73523E5C54 for ; Tue, 21 May 2013 05:35:26 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1369139314-3003-2-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > The docs say that the trickle feed disable bit is present (for primary > planes only, not video sprites) on CTG, and that it must be set > for ELK. Just set it for all g4x chipsets. > = > v2: Do it in init_clock_gating too Actually I just noticed that we don't set up this stuff in ironlake_init_clock_gating() either. Any opinions whether I should just kill the per-plane trickle feed stuff from *_init_clock_gating(), or should I add it to ironlake_init_clock_gating() as well? > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_display.c | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 9 +++++++++ > 2 files changed, 12 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 684ab64..c8b033a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2041,6 +2041,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc,= struct drm_framebuffer *fb, > dspcntr &=3D ~DISPPLANE_TILED; > } > = > + if (IS_G4X(dev)) > + dspcntr |=3D DISPPLANE_TRICKLE_FEED_DISABLE; > + > I915_WRITE(reg, dspcntr); > = > linear_offset =3D y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 8a90cf3..cf0f658 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4390,6 +4390,7 @@ static void g4x_init_clock_gating(struct drm_device= *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > uint32_t dspclk_gate; > + int pipe; > = > I915_WRITE(RENCLK_GATE_D1, 0); > I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | > @@ -4406,6 +4407,14 @@ static void g4x_init_clock_gating(struct drm_devic= e *dev) > /* WaDisableRenderCachePipelinedFlush */ > I915_WRITE(CACHE_MODE_0, > _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); > + > + for_each_pipe(pipe) { > + I915_WRITE(DSPCNTR(pipe), > + I915_READ(DSPCNTR(pipe)) | > + DISPPLANE_TRICKLE_FEED_DISABLE); > + intel_flush_display_plane(dev_priv, pipe); > + } > + > } > = > static void crestline_init_clock_gating(struct drm_device *dev) > -- = > 1.8.1.5 -- = Ville Syrj=E4l=E4 Intel OTC