Patch: Increase maximum bus memory window size (for Xeon Phi)

[Bryce Lelbach <blelbach@cct.lsu.edu>]

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The attached patch affects pbus_size_mem() in drivers/pci/setup-bus.c. The patch
increases the maximum memory window size for a PCI bus from 2 Gb to 2^63 Gb.

This change is necessary to support Intel Xeon Phi co-processors. These co-processors
are PCIe devices used for high-performance computing applications. The device requires
an 8Gb memory window to function (the co-processor has 8Gb of onboard memory).

This patch is a modified version of a patch from Intel's MPSS framework
(specifically, from the "KNC_gold_update_1-2.1.4982-15-rhel-6.3" package), which
will apply to a 3.7.8 kernel (I am about to try it on a 3.8 kernel). To the best
of my knowledge, newer RHEL kernels are shipped with this patch.
 
-- 
Bryce Adelstein-Lelbach aka wash
STE||AR Group, Center for Computation and Technology, LSU
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diff -u -r -N linux-source-3.7/drivers/pci/setup-bus.c linux-source-3.7-xeon-phi/drivers/pci/setup-bus.c
--- linux-source-3.7/drivers/pci/setup-bus.c	2013-02-14 12:57:59.000000000 -0600
+++ linux-source-3.7-xeon-phi/drivers/pci/setup-bus.c	2013-02-20 18:08:16.000000000 -0600
@@ -852,7 +852,7 @@
 {
 	struct pci_dev *dev;
 	resource_size_t min_align, align, size, size0, size1;
-	resource_size_t aligns[12];	/* Alignments from 1Mb to 2Gb */
+	resource_size_t aligns[44];	/* Alignments from 1Mb to 2^63 */
 	int order, max_order;
 	struct resource *b_res = find_free_bus_resource(bus, type);
 	unsigned int mem64_mask = 0;
@@ -891,7 +891,8 @@
 			/* For bridges size != alignment */
 			align = pci_resource_alignment(dev, r);
 			order = __ffs(align) - 20;
-			if (order > 11) {
+			if ((sizeof(size_t) == 4 && order > 11) ||
+					(sizeof(size_t) == 8 && order > 43)) {
 				dev_warn(&dev->dev, "disabling BAR %d: %pR "
 					 "(bad alignment %#llx)\n", i, r,
 					 (unsigned long long) align);

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