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From: Andi Kleen <andi@firstfloor.org>
To: Stephane Eranian <eranian@google.com>
Cc: Andi Kleen <andi@firstfloor.org>, Ingo Molnar <mingo@kernel.org>,
	LKML <linux-kernel@vger.kernel.org>,
	Peter Zijlstra <a.p.zijlstra@chello.nl>,
	Andrew Morton <akpm@linux-foundation.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 1/5] perf, x86: Add Haswell PEBS record support v5
Date: Fri, 31 May 2013 18:23:12 +0200	[thread overview]
Message-ID: <20130531162312.GO6123@two.firstfloor.org> (raw)
In-Reply-To: <CABPqkBSuiWCLyXkNhuq6wXFP2G+4rOQv_H4134R55CqcVFAAUA@mail.gmail.com>

On Fri, May 31, 2013 at 03:02:29PM +0200, Stephane Eranian wrote:
> Hi,
> 
> So looked at this patch again. There is nothing wrong with the code.
> But there is something bothering me with the usage model. I think
> the choice of having pebs->ip for precise=1 or pebs->real_ip for
> precise=2 is too restrictive.
> 
> There are situations where you want BOTH the real_ip AND the
> off-by-one ip. This is when you're sampling call branches.
> The real_ip gives you the call site, the off-by-one gives you
> the target of the branch. This is very handy because you do
> not need to use the LBR to get this, unlike with SandyBridge.

It's also useful for TSX: critical section versus abort point
inside transaction.

> So we need to find an extension or a way to return both IPs
> without invoking LBR. Easiest would be to add another
> PERF_SAMPLE_*.
> 
> Any better idea?

For TSX I just use two different events. It works.

I'm not disagreeing with it, but I think it's an orthogonal issue to my
patchkit.   Adding a new SAMPLE type seems reasonable to me.

-Andi

  reply	other threads:[~2013-05-31 16:23 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-21 19:59 Basic perf PMU support for Haswell v10 Andi Kleen
2013-03-21 19:59 ` [PATCH 1/5] perf, x86: Add Haswell PEBS record support v5 Andi Kleen
2013-05-31 13:02   ` Stephane Eranian
2013-05-31 16:23     ` Andi Kleen [this message]
2013-03-21 19:59 ` [PATCH 2/5] perf, x86: Basic Haswell PMU support v7 Andi Kleen
2013-03-21 19:59 ` [PATCH 3/5] perf, x86: Basic Haswell PEBS support v4 Andi Kleen
2013-03-21 19:59 ` [PATCH 4/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-03-21 19:59 ` [PATCH 5/5] perf, x86: Support Haswell v4 LBR format Andi Kleen
2013-03-28 15:13 ` Basic perf PMU support for Haswell v10 Stephane Eranian
2013-04-05  6:46 ` Ingo Molnar
2013-04-15 10:36   ` Ingo Molnar
2013-05-27 13:01     ` Stephane Eranian
2013-05-27 19:18       ` Andi Kleen
  -- strict thread matches above, loose matches on Subject: below --
2013-04-20 19:06 Basic perf PMU support for Haswell v11 Andi Kleen
2013-04-20 19:06 ` [PATCH 1/5] perf, x86: Add Haswell PEBS record support v5 Andi Kleen

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