From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: WA: FBC Render Nuke. Date: Tue, 4 Jun 2013 10:06:08 +0300 Message-ID: <20130604070608.GD5004@intel.com> References: <20130603170340.GC5004@intel.com> <1370284909-2106-1-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 3BACBE5D0E for ; Tue, 4 Jun 2013 00:06:14 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1370284909-2106-1-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Jun 03, 2013 at 03:41:49PM -0300, Rodrigo Vivi wrote: > WaFbcNukeOn3DBlt for IVB, HSW. > = > According BSPec: "Workaround: Do not enable Render Command Streamer track= ing for FBC. > Instead insert a LRI to address 0x50380 with data 0x00000004 after the PI= PE_CONTROL that > follows each render submission." > = > v2: Chris noticed that flush_domains check was missing here and also sugg= ested to do > LRI only when fbc is enabled. To avoid do a I915_READ on every flush = lets use the > module parameter check. > = > v3: Adding Wa name as Damien suggested. > = > v4: Ville noticed VLV doesn't support fbc at all and comment came wrong f= rom spec. > = > v5: Ville noticed than on blt a Cache Clean LRI should be used instead th= e Nuke one. > = > Cc: Ville Syrj=E4l=E4 > Cc: Chris Wilson > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 32 +++++++++++++++++++++++++++= +++++ > 3 files changed, 36 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index cc4c223..f37ddee 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -977,6 +977,9 @@ > /* Framebuffer compression for Ivybridge */ > #define IVB_FBC_RT_BASE 0x7020 > = > +#define MSG_FBC_REND_STATE 0x50380 > +#define FBC_REND_NUKE (1<<2) > +#define FBC_REND_CACHE_CLEAN (1<<1) > = > #define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 > #define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 1879188..e830a9b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -274,7 +274,7 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, un= signed long interval) > struct drm_i915_gem_object *obj =3D intel_fb->obj; > struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > = > - I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); > + I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset); > = > if (!intel_edp_is_psr_enabled(dev)) > I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X | > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 3d2c236..3e24639 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -280,6 +280,30 @@ gen7_render_ring_cs_stall_wa(struct intel_ring_buffe= r *ring) > return 0; > } > = > +static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, bool nuke) > +{ > + struct drm_device *dev =3D ring->dev; > + int ret; > + > + if (i915_enable_fbc =3D=3D 0) > + return 0; > + > + if (i915_enable_fbc < 0 && !IS_HASWELL(dev)) > + return 0; > + > + ret =3D intel_ring_begin(ring, 4); > + if (ret) > + return ret; > + intel_ring_emit(ring, MI_NOOP); > + /* WaFbcNukeOn3DBlt:ivb/hsw */ > + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); > + intel_ring_emit(ring, MSG_FBC_REND_STATE); > + intel_ring_emit(ring, nuke ? FBC_REND_NUKE : FBC_REND_CACHE_CLEAN); > + intel_ring_advance(ring); > + > + return 0; > +} > + > static int > gen7_render_ring_flush(struct intel_ring_buffer *ring, > u32 invalidate_domains, u32 flush_domains) > @@ -336,6 +360,9 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, > intel_ring_emit(ring, 0); > intel_ring_advance(ring); > = > + if (flush_domains) > + return gen7_ring_fbc_flush(ring, true); > + > return 0; > } > = > @@ -1623,6 +1650,7 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buf= fer *ring, > static int blt_ring_flush(struct intel_ring_buffer *ring, > u32 invalidate, u32 flush) > { > + struct drm_device *dev =3D ring->dev; > uint32_t cmd; > int ret; > = > @@ -1645,6 +1673,10 @@ static int blt_ring_flush(struct intel_ring_buffer= *ring, > intel_ring_emit(ring, 0); > intel_ring_emit(ring, MI_NOOP); > intel_ring_advance(ring); > + > + if (IS_GEN7(dev)) > + return gen7_ring_fbc_flush(ring, false); Still no flush_domains check? Oh and looks like you need to rebase the patch since these functions got renamed. > + > return 0; > } > = > -- = > 1.7.11.7 -- = Ville Syrj=E4l=E4 Intel OTC