From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/2] drm/i915: Fix DSPCLK_GATE_D for VLV Date: Wed, 5 Jun 2013 10:01:04 +0200 Message-ID: <20130605080104.GF15743@phenom.ffwll.local> References: <1369148510-22461-1-git-send-email-ville.syrjala@linux.intel.com> <1369148510-22461-3-git-send-email-ville.syrjala@linux.intel.com> <87mwr5m23i.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f174.google.com (mail-ea0-f174.google.com [209.85.215.174]) by gabe.freedesktop.org (Postfix) with ESMTP id 1E38BE5D1A for ; Wed, 5 Jun 2013 01:01:09 -0700 (PDT) Received: by mail-ea0-f174.google.com with SMTP id z7so898087eaf.5 for ; Wed, 05 Jun 2013 01:01:09 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87mwr5m23i.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Jun 05, 2013 at 10:46:41AM +0300, Jani Nikula wrote: > On Tue, 21 May 2013, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj=E4l=E4 > > > > Fix the DSPCLK_GATE_D access for VLV. The code incorrectly tried to > > poke at the ILK+ version of the register which is at the wrong offset. > = > Reviewed-by: Jani Nikula Both merged, thanks. -Daniel > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 +- > > drivers/gpu/drm/i915/intel_pm.c | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 55caedb..4e8aabd 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1208,7 +1208,7 @@ > > #define DSTATE_PLL_D3_OFF (1<<3) > > #define DSTATE_GFX_CLOCK_GATING (1<<1) > > #define DSTATE_DOT_CLOCK_GATING (1<<0) > > -#define DSPCLK_GATE_D 0x6200 > > +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200) > > # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ > > # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ > > # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index a1a931c..4c8ce90 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4284,7 +4284,7 @@ static void valleyview_init_clock_gating(struct d= rm_device *dev) > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > int pipe; > > = > > - I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); > > + I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > > = > > /* WaDisableEarlyCull:vlv */ > > I915_WRITE(_3D_CHICKEN3, > > -- = > > 1.8.1.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Jani Nikula, Intel Open Source Technology Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch