From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Hemminger Subject: Re: [PATCH 5/7] pci: support multiple PCI regions per device Date: Wed, 5 Jun 2013 14:33:37 -0700 Message-ID: <20130605143337.76af91ff@nehalam.linuxnetplumber.net> References: <20130530171234.301927271@vyatta.com> <20130530171627.005239011@vyatta.com> <51AF501B.5060306@6wind.com> <20130605084927.34f138c1@nehalam.linuxnetplumber.net> <51AF7DDB.1070005@6wind.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: dev-VfR2kkLFssw@public.gmane.org To: Damien Millescamps Return-path: In-Reply-To: <51AF7DDB.1070005-pdR9zngts4EAvxtiuMwx3w@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" On Wed, 05 Jun 2013 20:05:15 +0200 Damien Millescamps wrote: > On 06/05/2013 05:49 PM, Stephen Hemminger wrote: > > On Wed, 05 Jun 2013 16:50:03 +0200 > > Damien Millescamps wrote: > > > >> Hi Stephen, > >> > >> Overall this patch is very nice. My only comment on this one is why do > >> you limit the max number of memory resources to 5 ? > >> The PCI configuration space permits to store up to 6 base addresses. > >> > >>> +#define PCI_MEM_RESOURCE 5 > >> Please, can you add a log/comment with your patch, too ? > >> > >> > >> Cheers, > > Only because I was trying to save some space, and I didn't see any hardware > > with that many useful regions. Also the kernel UIO driver has some control > > over which regions get exposed. > > I agree that hardware generally don't use that much BAR for the PCIe. > However, this is only a matter of 20 to 24 Bytes, so I don't see any > reason not defining this macro as per the PCI standard value. > > Could you add a commit log and change that so it can be ack'd and pushed > in the DPDK repository ? > > Thanks, Go ahead and change the 5 to a 7. No point in another resend of whole pile.