From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH] drm/i915: VGA also requires the power well
Date: Thu, 6 Jun 2013 11:38:04 +0300 [thread overview]
Message-ID: <20130606083804.GM5004@intel.com> (raw)
In-Reply-To: <1370466351-3683-1-git-send-email-przanoni@gmail.com>
On Wed, Jun 05, 2013 at 06:05:51PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> So add a power domain and check for it before we try to read
> VGA_CONTROL.
>
> This fixes unclaimed register messages that happen on suspend/resume.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> 3 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 46b1f70..d51ce13 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -89,6 +89,7 @@ enum port {
> #define port_name(p) ((p) + 'A')
>
> enum intel_display_power_domain {
> + POWER_DOMAIN_VGA,
> POWER_DOMAIN_PIPE_A,
> POWER_DOMAIN_PIPE_B,
> POWER_DOMAIN_PIPE_C,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4c8fcec..3719d99 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9950,6 +9950,9 @@ void i915_redisable_vga(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 vga_reg = i915_vgacntrl_reg(dev);
>
> + if (!intel_display_power_enabled(dev, POWER_DOMAIN_VGA))
> + return;
> +
So it looks like you're essentially making intel_redisable_vga() a nop
for HSW. Shouldn't we instead enable the power well during resume?
> if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
> DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> i915_disable_vga(dev);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 50fe3d7..47ef4a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5000,6 +5000,7 @@ bool intel_display_power_enabled(struct drm_device *dev,
> case POWER_DOMAIN_PIPE_A:
> case POWER_DOMAIN_TRANSCODER_EDP:
> return true;
> + case POWER_DOMAIN_VGA:
> case POWER_DOMAIN_PIPE_B:
> case POWER_DOMAIN_PIPE_C:
> case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
> --
> 1.8.1.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2013-06-06 8:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-05 21:05 [PATCH] drm/i915: VGA also requires the power well Paulo Zanoni
2013-06-06 8:38 ` Ville Syrjälä [this message]
2013-06-06 14:35 ` Paulo Zanoni
2013-06-06 14:47 ` Ville Syrjälä
2013-08-02 17:17 ` Paulo Zanoni
2013-08-02 17:17 ` Paulo Zanoni
2013-08-04 19:49 ` Daniel Vetter
2013-08-12 18:06 ` Zanoni, Paulo R
2013-08-14 14:41 ` Daniel Vetter
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