From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 03/31] drm/i915: lock down pch pll accouting some more Date: Fri, 7 Jun 2013 22:03:20 +0200 Message-ID: <20130607200320.GA22870@phenom.ffwll.local> References: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> <1370432073-27634-4-git-send-email-daniel.vetter@ffwll.ch> <20130607163256.GR5004@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f174.google.com (mail-ea0-f174.google.com [209.85.215.174]) by gabe.freedesktop.org (Postfix) with ESMTP id 0962AE5C7A for ; Fri, 7 Jun 2013 13:05:11 -0700 (PDT) Received: by mail-ea0-f174.google.com with SMTP id o10so732923eaj.33 for ; Fri, 07 Jun 2013 13:05:11 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130607163256.GR5004@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Fri, Jun 07, 2013 at 07:32:56PM +0300, Ville Syrj=E4l=E4 wrote: > On Wed, Jun 05, 2013 at 01:34:05PM +0200, Daniel Vetter wrote: > > Before I start to make a complete mess out of this, crank up > > the paranoia level a bit. > > = > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/intel_display.c | 9 ++++++++- > > 1 file changed, 8 insertions(+), 1 deletion(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index 56fb6ed..39e977f 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct intel_cr= tc *intel_crtc) > > } > > = > > assert_pch_pll_enabled(dev_priv, pll, NULL); > > + WARN_ON(!pll->on); > > if (--pll->active) > > return; > = > Maybe a WARN_ON(pll->on) near the end of ironlake_enable_pch_pll() too? At the very end we set on =3D true, and the only non-error early return (when the active refcount is > 0 to begin with) has alreay a WARN_ON(!pll->on). Shouldn't that be good enough? > = > > = > > @@ -3031,12 +3032,18 @@ static void intel_put_pch_pll(struct intel_crtc= *intel_crtc) > > if (pll =3D=3D NULL) > > return; > > = > > + WARN_ON(!intel_crtc->config.has_pch_encoder); > = > Doesn't that trigger if we switch directly from PCH to CPU eDP? I've missed this case in testing somehow, and it's indeed broken. I don't hit the WARN here, but that's just because I've broken the refcounting somewhere. At least I've got plenty of backtraces, so the level of paranoia seems to be correct ;-) I'll fix this up and resend. -Daniel > = > > + > > if (pll->refcount =3D=3D 0) { > > WARN(1, "bad PCH PLL refcount\n"); > > return; > > } > > = > > - --pll->refcount; > > + if (--pll->refcount =3D=3D 0) { > > + WARN_ON(pll->on); > > + WARN_ON(pll->active); > > + } > > + > > intel_crtc->pch_pll =3D NULL; > > } > > = > > -- = > > 1.7.11.7 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Ville Syrj=E4l=E4 > Intel OTC -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch