From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e9.ny.us.ibm.com (e9.ny.us.ibm.com [32.97.182.139]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e9.ny.us.ibm.com", Issuer "GeoTrust SSL CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 562DF2C007B for ; Tue, 11 Jun 2013 07:49:51 +1000 (EST) Received: from /spool/local by e9.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 10 Jun 2013 17:49:48 -0400 Received: from d01relay04.pok.ibm.com (d01relay04.pok.ibm.com [9.56.227.236]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id DD77DC90068 for ; Mon, 10 Jun 2013 17:49:31 -0400 (EDT) Received: from d03av01.boulder.ibm.com (d03av01.boulder.ibm.com [9.17.195.167]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r5ALnWlF224732 for ; Mon, 10 Jun 2013 17:49:32 -0400 Received: from d03av01.boulder.ibm.com (loopback [127.0.0.1]) by d03av01.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r5ALnVK8027547 for ; Mon, 10 Jun 2013 15:49:31 -0600 Date: Mon, 10 Jun 2013 14:48:48 -0700 From: Sukadev Bhattiprolu To: Anshuman Khandual Subject: Re: [PATCH 1/2] perf/Power7: Save dcache_src fields in sample record. Message-ID: <20130610214848.GA2666@us.ibm.com> References: <20130607204008.GA3281@us.ibm.com> <51B58843.5020809@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <51B58843.5020809@linux.vnet.ibm.com> Cc: Anton Blanchard , linux-kernel@vger.kernel.org, Stephane Eranian , linuxppc-dev@ozlabs.org, Paul Mackerras , mingo@kernel.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Anshuman Khandual [khandual@linux.vnet.ibm.com] wrote: | > The former approach seems less confusing and this patch uses that approach. | > | | Yeah, the former approach is simpler and makes sense. Ok. Seems to make sense at least on Power. | > + * We use the table, dcache_src_map, to map this value 1 to PERF_MEM_LVL_L3, | > + * the arch-neutral representation of the L3 cache. | > + * | > + * Similarly, in case of marked data TLB miss, bits 14..17 of the MMCRA | > + * indicate the load source of a marked DTLB entry. dtlb_src_map[] gives | > + * the mapping to the arch-neutral values of the TLB source. | | | Where did you define dtlb_src_map[] ? Ah, the comment belongs in another patch that I am working on. That patch maps the PERF_MEM_TLB* flags to Power7. Thanks for the comments. Sukadev From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753955Ab3FJVtg (ORCPT ); Mon, 10 Jun 2013 17:49:36 -0400 Received: from e31.co.us.ibm.com ([32.97.110.149]:42739 "EHLO e31.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753285Ab3FJVte (ORCPT ); Mon, 10 Jun 2013 17:49:34 -0400 Date: Mon, 10 Jun 2013 14:48:48 -0700 From: Sukadev Bhattiprolu To: Anshuman Khandual Cc: mingo@kernel.org, Paul Mackerras , linuxppc-dev@ozlabs.org, Anton Blanchard , linux-kernel@vger.kernel.org, Stephane Eranian Subject: Re: [PATCH 1/2] perf/Power7: Save dcache_src fields in sample record. Message-ID: <20130610214848.GA2666@us.ibm.com> References: <20130607204008.GA3281@us.ibm.com> <51B58843.5020809@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <51B58843.5020809@linux.vnet.ibm.com> X-Operating-System: Linux 2.0.32 on an i486 User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13061021-7282-0000-0000-0000182310F1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Anshuman Khandual [khandual@linux.vnet.ibm.com] wrote: | > The former approach seems less confusing and this patch uses that approach. | > | | Yeah, the former approach is simpler and makes sense. Ok. Seems to make sense at least on Power. | > + * We use the table, dcache_src_map, to map this value 1 to PERF_MEM_LVL_L3, | > + * the arch-neutral representation of the L3 cache. | > + * | > + * Similarly, in case of marked data TLB miss, bits 14..17 of the MMCRA | > + * indicate the load source of a marked DTLB entry. dtlb_src_map[] gives | > + * the mapping to the arch-neutral values of the TLB source. | | | Where did you define dtlb_src_map[] ? Ah, the comment belongs in another patch that I am working on. That patch maps the PERF_MEM_TLB* flags to Power7. Thanks for the comments. Sukadev