diff for duplicates of <201306111331.31517.heiko@sntech.de> diff --git a/a/1.txt b/N1/1.txt index 78602f0..9b00f5f 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -6,7 +6,7 @@ The plls are currently read-only, as their setting needs more investigation. This also results in slow cpu speeds, as the apll starts at a default of 600mhz. -Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> +Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/arm/boot/dts/rk3066a-clocks.dtsi | 467 +++++++++++++++++++++++++++++++ drivers/clk/Makefile | 1 + @@ -29,7 +29,7 @@ index 0000000..d797710 @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -67,7 +67,7 @@ index 0000000..d797710 + #clock-cells = <0>; + }; + -+ apll: apll@20000000 { ++ apll: apll at 20000000 { + compatible = "rockchip,rk3066a-apll"; + reg = <0x20000000 0x10>, + <0x20000040 0x04>; @@ -75,7 +75,7 @@ index 0000000..d797710 + #clock-cells = <0>; + }; + -+ dpll: dpll@20000000 { ++ dpll: dpll at 20000000 { + compatible = "rockchip,rk3066a-dpll"; + reg = <0x20000010 0x10>, + <0x20000040 0x04>; @@ -83,7 +83,7 @@ index 0000000..d797710 + #clock-cells = <0>; + }; + -+ cpll: cpll@20000000 { ++ cpll: cpll at 20000000 { + compatible = "rockchip,rk3066a-cpll"; + reg = <0x20000020 0x10>, + <0x20000040 0x04>; @@ -91,7 +91,7 @@ index 0000000..d797710 + #clock-cells = <0>; + }; + -+ gpll: gpll@20000000 { ++ gpll: gpll at 20000000 { + compatible = "rockchip,rk3066a-gpll"; + reg = <0x20000030 0x10>, + <0x20000040 0x04>; @@ -99,154 +99,154 @@ index 0000000..d797710 + #clock-cells = <0>; + }; + -+ mux_aclk_periph: mux-aclk-periph@2000006c { ++ mux_aclk_periph: mux-aclk-periph at 2000006c { + compatible = "rockchip,rk2928-gpll-cpll-bit15-mux"; + reg = <0x2000006c 0x04>; + clocks = <&gpll>, <&cpll>; + #clock-cells = <0>; + }; + -+ mux_uart_pll: mux-uart_pll@20000074 { ++ mux_uart_pll: mux-uart_pll at 20000074 { + compatible = "rockchip,rk2928-gpll-cpll-bit15-mux"; + reg = <0x20000074 0x04>; + clocks = <&gpll>, <&cpll>; + #clock-cells = <0>; + }; + -+ div_uart0: div-uart0@20000078 { ++ div_uart0: div-uart0 at 20000078 { + compatible = "rockchip,rk2928-uart-divider"; + reg = <0x20000078 0x04>; + clocks = <&mux_uart_pll>; + #clock-cells = <0>; + }; + -+ mux_uart0: mux-uart0@20000078 { ++ mux_uart0: mux-uart0 at 20000078 { + compatible = "rockchip,rk2928-uart-mux"; + reg = <0x20000078 0x04>; + clocks = <&clk_gates1 8>, <&dummy>, <&xin24m>; /* dummy is uart0_frac_div */ + #clock-cells = <0>; + }; + -+ div_uart1: div-uart1@2000007c { ++ div_uart1: div-uart1 at 2000007c { + compatible = "rockchip,rk2928-uart-divider"; + reg = <0x2000007c 0x04>; + clocks = <&mux_uart_pll>; + #clock-cells = <0>; + }; + -+ mux_uart1: mux-uart1@2000007c { ++ mux_uart1: mux-uart1 at 2000007c { + compatible = "rockchip,rk2928-uart-mux"; + reg = <0x2000007c 0x04>; + clocks = <&clk_gates1 10>, <&dummy>, <&xin24m>; + #clock-cells = <0>; + }; + -+ div_uart2: div-uart2@20000080 { ++ div_uart2: div-uart2 at 20000080 { + compatible = "rockchip,rk2928-uart-divider"; + reg = <0x20000080 0x04>; + clocks = <&mux_uart_pll>; + #clock-cells = <0>; + }; + -+ mux_uart2: mux-uart2@20000080 { ++ mux_uart2: mux-uart2 at 20000080 { + compatible = "rockchip,rk2928-uart-mux"; + reg = <0x20000080 0x04>; + clocks = <&clk_gates1 12>, <&dummy>, <&xin24m>; + #clock-cells = <0>; + }; + -+ div_uart3: div-uart3@20000084 { ++ div_uart3: div-uart3 at 20000084 { + compatible = "rockchip,rk2928-uart-divider"; + reg = <0x20000084 0x04>; + clocks = <&mux_uart_pll>; + #clock-cells = <0>; + }; + -+ mux_uart3: mux-uart3@20000084 { ++ mux_uart3: mux-uart3 at 20000084 { + compatible = "rockchip,rk2928-uart-mux"; + reg = <0x20000084 0x04>; + clocks = <&clk_gates1 14>, <&dummy>, <&xin24m>; + #clock-cells = <0>; + }; + -+ mux_cpu: mux-cpu@20000044 { ++ mux_cpu: mux-cpu at 20000044 { + compatible = "rockchip,rk3066-cpu-mux"; + reg = <0x20000044 0x4>; + clocks = <&apll>, <&dummy> /* cpu_gpll_path */; + #clock-cells = <0>; + }; + -+ div_cpu: div-cpu@20000044 { ++ div_cpu: div-cpu at 20000044 { + compatible = "rockchip,rk3066a-cpu-divider"; + reg = <0x20000044 0x4>; + clocks = <&mux_cpu>; + #clock-cells = <0>; + }; + -+ div_core_periph: div-core-periph@20000044 { ++ div_core_periph: div-core-periph at 20000044 { + compatible = "rockchip,rk3066a-core-periph-divider"; + reg = <0x20000044 0x4>; + clocks = <&div_cpu>; + #clock-cells = <0>; + }; + -+ div_aclk_cpu: div-aclk-cpu@20000048 { ++ div_aclk_cpu: div-aclk-cpu at 20000048 { + compatible = "rockchip,rk3066a-aclk-cpu-divider"; + reg = <0x20000048 0x4>; + clocks = <&div_cpu>; + #clock-cells = <0>; + }; + -+ div_aclk_periph: div-aclk-periph@2000006c { ++ div_aclk_periph: div-aclk-periph at 2000006c { + compatible = "rockchip,rk2928-aclk-periph-divider"; + reg = <0x2000006c 0x4>; + clocks = <&mux_aclk_periph>; + #clock-cells = <0>; + }; + -+ div_hclk_periph: div-hclk-periph@2000006c { ++ div_hclk_periph: div-hclk-periph at 2000006c { + compatible = "rockchip,rk2928-hclk-divider"; + reg = <0x2000006c 0x4>; + clocks = <&clk_gates2 1>; + #clock-cells = <0>; + }; + -+ div_pclk_periph: div-pclk-periph@2000006c { ++ div_pclk_periph: div-pclk-periph at 2000006c { + compatible = "rockchip,rk2928-pclk-divider"; + reg = <0x2000006c 0x4>; + clocks = <&clk_gates2 1>; + #clock-cells = <0>; + }; + -+ div_hclk_cpu: div-hclk-cpu@20000048 { ++ div_hclk_cpu: div-hclk-cpu at 20000048 { + compatible = "rockchip,rk2928-hclk-divider"; + reg = <0x20000048 0x4>; + clocks = <&clk_gates0 3>; + #clock-cells = <0>; + }; + -+ div_pclk_cpu: div-pclk-cpu@20000048 { ++ div_pclk_cpu: div-pclk-cpu at 20000048 { + compatible = "rockchip,rk2928-pclk-divider"; + reg = <0x20000048 0x4>; + clocks = <&clk_gates0 3>; + #clock-cells = <0>; + }; + -+ div_mmc0: div-mmc0@20000070 { ++ div_mmc0: div-mmc0 at 20000070 { + compatible = "rockchip,rk2928-mmc-divider"; + reg = <0x20000070 0x4>; + clocks = <&clk_gates2 2>; + #clock-cells = <0>; + }; + -+ div_mmc1: div-mmc1@20000074 { ++ div_mmc1: div-mmc1 at 20000074 { + compatible = "rockchip,rk2928-mmc-divider"; + reg = <0x20000074 0x4>; + clocks = <&clk_gates2 2>; + #clock-cells = <0>; + }; + -+ clk_gates0: gate-clk@200000d0 { ++ clk_gates0: gate-clk at 200000d0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d0 0x4>; + clocks = <&dummy>, <&dummy>, @@ -271,7 +271,7 @@ index 0000000..d797710 + #clock-cells = <1>; + }; + -+ clk_gates1: gate-clk@200000d4 { ++ clk_gates1: gate-clk at 200000d4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d4 0x4>; + clocks = <&xin24m>, <&xin24m>, @@ -296,7 +296,7 @@ index 0000000..d797710 + #clock-cells = <1>; + }; + -+ clk_gates2: gate-clk@200000d8 { ++ clk_gates2: gate-clk at 200000d8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d8 0x4>; + clocks = <&clk_gates2 1>, <&div_aclk_periph>, @@ -321,7 +321,7 @@ index 0000000..d797710 + #clock-cells = <1>; + }; + -+ clk_gates3: gate-clk@200000dc { ++ clk_gates3: gate-clk at 200000dc { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000dc 0x4>; + clocks = <&dummy>, <&dummy>, @@ -346,7 +346,7 @@ index 0000000..d797710 + #clock-cells = <1>; + }; + -+ clk_gates4: gate-clk@200000e0 { ++ clk_gates4: gate-clk at 200000e0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e0 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates2 3>, @@ -371,7 +371,7 @@ index 0000000..d797710 + #clock-cells = <1>; + }; + -+ clk_gates5: gate-clk@200000e4 { ++ clk_gates5: gate-clk at 200000e4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e4 0x4>; + clocks = <&clk_gates0 3>, <&clk_gates2 1>, @@ -396,7 +396,7 @@ index 0000000..d797710 + #clock-cells = <1>; + }; + -+ clk_gates6: gate-clk@200000e8 { ++ clk_gates6: gate-clk at 200000e8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e8 0x4>; + clocks = <&clk_gates3 0>, <&clk_gates0 4>, @@ -421,7 +421,7 @@ index 0000000..d797710 + #clock-cells = <1>; + }; + -+ clk_gates7: gate-clk@200000ec { ++ clk_gates7: gate-clk at 200000ec { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000ec 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates0 4>, @@ -446,7 +446,7 @@ index 0000000..d797710 + #clock-cells = <1>; + }; + -+ clk_gates8: gate-clk@200000f0 { ++ clk_gates8: gate-clk at 200000f0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f0 0x4>; + clocks = <&clk_gates0 5>, <&clk_gates0 5>, @@ -471,7 +471,7 @@ index 0000000..d797710 + #clock-cells = <1>; + }; + -+ clk_gates9: gate-clk@200000f4 { ++ clk_gates9: gate-clk at 200000f4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f4 0x4>; + clocks = <&dummy>, <&clk_gates0 5>, @@ -526,7 +526,7 @@ index 0000000..4456445 @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -663,7 +663,7 @@ index 0000000..a63288a @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -688,7 +688,7 @@ index 0000000..660b00f @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by diff --git a/a/content_digest b/N1/content_digest index 6546e91..b4ceb41 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,20 +1,8 @@ "ref\0201306111328.52679.heiko@sntech.de\0" - "ref\0201306111328.52679.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org\0" - "From\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" + "From\0heiko@sntech.de (Heiko St\303\274bner)\0" "Subject\0[PATCH v3 5/7] clk: add basic Rockchip rk3066a clock support\0" "Date\0Tue, 11 Jun 2013 13:31:31 +0200\0" - "To\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" - "Cc\0Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>" - Seungwon Jeon <tgih.jun-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> - linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org> - Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> - Andy Shevchenko <andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> - Chris Ball <cjb-2X9k7bc8m7Mdnm+yROfE0A@public.gmane.org> - " devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "This adds basic support for clocks on Rockchip rk3066 SoCs.\n" @@ -25,7 +13,7 @@ "investigation. This also results in slow cpu speeds, as the apll starts\n" "at a default of 600mhz.\n" "\n" - "Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "Signed-off-by: Heiko Stuebner <heiko@sntech.de>\n" "---\n" " arch/arm/boot/dts/rk3066a-clocks.dtsi | 467 +++++++++++++++++++++++++++++++\n" " drivers/clk/Makefile | 1 +\n" @@ -48,7 +36,7 @@ "@@ -0,0 +1,467 @@\n" "+/*\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -86,7 +74,7 @@ "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tapll: apll@20000000 {\n" + "+\t\tapll: apll at 20000000 {\n" "+\t\t\tcompatible = \"rockchip,rk3066a-apll\";\n" "+\t\t\treg = <0x20000000 0x10>,\n" "+\t\t\t <0x20000040 0x04>;\n" @@ -94,7 +82,7 @@ "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdpll: dpll@20000000 {\n" + "+\t\tdpll: dpll at 20000000 {\n" "+\t\t\tcompatible = \"rockchip,rk3066a-dpll\";\n" "+\t\t\treg = <0x20000010 0x10>,\n" "+\t\t\t <0x20000040 0x04>;\n" @@ -102,7 +90,7 @@ "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpll: cpll@20000000 {\n" + "+\t\tcpll: cpll at 20000000 {\n" "+\t\t\tcompatible = \"rockchip,rk3066a-cpll\";\n" "+\t\t\treg = <0x20000020 0x10>,\n" "+\t\t\t <0x20000040 0x04>;\n" @@ -110,7 +98,7 @@ "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tgpll: gpll@20000000 {\n" + "+\t\tgpll: gpll at 20000000 {\n" "+\t\t\tcompatible = \"rockchip,rk3066a-gpll\";\n" "+\t\t\treg = <0x20000030 0x10>,\n" "+\t\t\t <0x20000040 0x04>;\n" @@ -118,154 +106,154 @@ "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tmux_aclk_periph: mux-aclk-periph@2000006c {\n" + "+\t\tmux_aclk_periph: mux-aclk-periph at 2000006c {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gpll-cpll-bit15-mux\";\n" "+\t\t\treg = <0x2000006c 0x04>;\n" "+\t\t\tclocks = <&gpll>, <&cpll>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tmux_uart_pll: mux-uart_pll@20000074 {\n" + "+\t\tmux_uart_pll: mux-uart_pll at 20000074 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gpll-cpll-bit15-mux\";\n" "+\t\t\treg = <0x20000074 0x04>;\n" "+\t\t\tclocks = <&gpll>, <&cpll>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_uart0: div-uart0@20000078 {\n" + "+\t\tdiv_uart0: div-uart0 at 20000078 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-uart-divider\";\n" "+\t\t\treg = <0x20000078 0x04>;\n" "+\t\t\tclocks = <&mux_uart_pll>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tmux_uart0: mux-uart0@20000078 {\n" + "+\t\tmux_uart0: mux-uart0 at 20000078 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-uart-mux\";\n" "+\t\t\treg = <0x20000078 0x04>;\n" "+\t\t\tclocks = <&clk_gates1 8>, <&dummy>, <&xin24m>; /* dummy is uart0_frac_div */\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_uart1: div-uart1@2000007c {\n" + "+\t\tdiv_uart1: div-uart1 at 2000007c {\n" "+\t\t\tcompatible = \"rockchip,rk2928-uart-divider\";\n" "+\t\t\treg = <0x2000007c 0x04>;\n" "+\t\t\tclocks = <&mux_uart_pll>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tmux_uart1: mux-uart1@2000007c {\n" + "+\t\tmux_uart1: mux-uart1 at 2000007c {\n" "+\t\t\tcompatible = \"rockchip,rk2928-uart-mux\";\n" "+\t\t\treg = <0x2000007c 0x04>;\n" "+\t\t\tclocks = <&clk_gates1 10>, <&dummy>, <&xin24m>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_uart2: div-uart2@20000080 {\n" + "+\t\tdiv_uart2: div-uart2 at 20000080 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-uart-divider\";\n" "+\t\t\treg = <0x20000080 0x04>;\n" "+\t\t\tclocks = <&mux_uart_pll>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tmux_uart2: mux-uart2@20000080 {\n" + "+\t\tmux_uart2: mux-uart2 at 20000080 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-uart-mux\";\n" "+\t\t\treg = <0x20000080 0x04>;\n" "+\t\t\tclocks = <&clk_gates1 12>, <&dummy>, <&xin24m>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_uart3: div-uart3@20000084 {\n" + "+\t\tdiv_uart3: div-uart3 at 20000084 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-uart-divider\";\n" "+\t\t\treg = <0x20000084 0x04>;\n" "+\t\t\tclocks = <&mux_uart_pll>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tmux_uart3: mux-uart3@20000084 {\n" + "+\t\tmux_uart3: mux-uart3 at 20000084 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-uart-mux\";\n" "+\t\t\treg = <0x20000084 0x04>;\n" "+\t\t\tclocks = <&clk_gates1 14>, <&dummy>, <&xin24m>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tmux_cpu: mux-cpu@20000044 {\n" + "+\t\tmux_cpu: mux-cpu at 20000044 {\n" "+\t\t\tcompatible = \"rockchip,rk3066-cpu-mux\";\n" "+\t\t\treg = <0x20000044 0x4>;\n" "+\t\t\tclocks = <&apll>, <&dummy> /* cpu_gpll_path */;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_cpu: div-cpu@20000044 {\n" + "+\t\tdiv_cpu: div-cpu at 20000044 {\n" "+\t\t\tcompatible = \"rockchip,rk3066a-cpu-divider\";\n" "+\t\t\treg = <0x20000044 0x4>;\n" "+\t\t\tclocks = <&mux_cpu>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_core_periph: div-core-periph@20000044 {\n" + "+\t\tdiv_core_periph: div-core-periph at 20000044 {\n" "+\t\t\tcompatible = \"rockchip,rk3066a-core-periph-divider\";\n" "+\t\t\treg = <0x20000044 0x4>;\n" "+\t\t\tclocks = <&div_cpu>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_aclk_cpu: div-aclk-cpu@20000048 {\n" + "+\t\tdiv_aclk_cpu: div-aclk-cpu at 20000048 {\n" "+\t\t\tcompatible = \"rockchip,rk3066a-aclk-cpu-divider\";\n" "+\t\t\treg = <0x20000048 0x4>;\n" "+\t\t\tclocks = <&div_cpu>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_aclk_periph: div-aclk-periph@2000006c {\n" + "+\t\tdiv_aclk_periph: div-aclk-periph at 2000006c {\n" "+\t\t\tcompatible = \"rockchip,rk2928-aclk-periph-divider\";\n" "+\t\t\treg = <0x2000006c 0x4>;\n" "+\t\t\tclocks = <&mux_aclk_periph>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_hclk_periph: div-hclk-periph@2000006c {\n" + "+\t\tdiv_hclk_periph: div-hclk-periph at 2000006c {\n" "+\t\t\tcompatible = \"rockchip,rk2928-hclk-divider\";\n" "+\t\t\treg = <0x2000006c 0x4>;\n" "+\t\t\tclocks = <&clk_gates2 1>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_pclk_periph: div-pclk-periph@2000006c {\n" + "+\t\tdiv_pclk_periph: div-pclk-periph at 2000006c {\n" "+\t\t\tcompatible = \"rockchip,rk2928-pclk-divider\";\n" "+\t\t\treg = <0x2000006c 0x4>;\n" "+\t\t\tclocks = <&clk_gates2 1>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_hclk_cpu: div-hclk-cpu@20000048 {\n" + "+\t\tdiv_hclk_cpu: div-hclk-cpu at 20000048 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-hclk-divider\";\n" "+\t\t\treg = <0x20000048 0x4>;\n" "+\t\t\tclocks = <&clk_gates0 3>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_pclk_cpu: div-pclk-cpu@20000048 {\n" + "+\t\tdiv_pclk_cpu: div-pclk-cpu at 20000048 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-pclk-divider\";\n" "+\t\t\treg = <0x20000048 0x4>;\n" "+\t\t\tclocks = <&clk_gates0 3>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_mmc0: div-mmc0@20000070 {\n" + "+\t\tdiv_mmc0: div-mmc0 at 20000070 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-mmc-divider\";\n" "+\t\t\treg = <0x20000070 0x4>;\n" "+\t\t\tclocks = <&clk_gates2 2>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tdiv_mmc1: div-mmc1@20000074 {\n" + "+\t\tdiv_mmc1: div-mmc1 at 20000074 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-mmc-divider\";\n" "+\t\t\treg = <0x20000074 0x4>;\n" "+\t\t\tclocks = <&clk_gates2 2>;\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates0: gate-clk@200000d0 {\n" + "+\t\tclk_gates0: gate-clk at 200000d0 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000d0 0x4>;\n" "+\t\t\tclocks = <&dummy>, <&dummy>,\n" @@ -290,7 +278,7 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates1: gate-clk@200000d4 {\n" + "+\t\tclk_gates1: gate-clk at 200000d4 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000d4 0x4>;\n" "+\t\t\tclocks = <&xin24m>, <&xin24m>,\n" @@ -315,7 +303,7 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates2: gate-clk@200000d8 {\n" + "+\t\tclk_gates2: gate-clk at 200000d8 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000d8 0x4>;\n" "+\t\t\tclocks = <&clk_gates2 1>, <&div_aclk_periph>,\n" @@ -340,7 +328,7 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates3: gate-clk@200000dc {\n" + "+\t\tclk_gates3: gate-clk at 200000dc {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000dc 0x4>;\n" "+\t\t\tclocks = <&dummy>, <&dummy>,\n" @@ -365,7 +353,7 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates4: gate-clk@200000e0 {\n" + "+\t\tclk_gates4: gate-clk at 200000e0 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000e0 0x4>;\n" "+\t\t\tclocks = <&clk_gates2 2>, <&clk_gates2 3>,\n" @@ -390,7 +378,7 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates5: gate-clk@200000e4 {\n" + "+\t\tclk_gates5: gate-clk at 200000e4 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000e4 0x4>;\n" "+\t\t\tclocks = <&clk_gates0 3>, <&clk_gates2 1>,\n" @@ -415,7 +403,7 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates6: gate-clk@200000e8 {\n" + "+\t\tclk_gates6: gate-clk at 200000e8 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000e8 0x4>;\n" "+\t\t\tclocks = <&clk_gates3 0>, <&clk_gates0 4>,\n" @@ -440,7 +428,7 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates7: gate-clk@200000ec {\n" + "+\t\tclk_gates7: gate-clk at 200000ec {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000ec 0x4>;\n" "+\t\t\tclocks = <&clk_gates2 2>, <&clk_gates0 4>,\n" @@ -465,7 +453,7 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates8: gate-clk@200000f0 {\n" + "+\t\tclk_gates8: gate-clk at 200000f0 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000f0 0x4>;\n" "+\t\t\tclocks = <&clk_gates0 5>, <&clk_gates0 5>,\n" @@ -490,7 +478,7 @@ "+\t\t\t#clock-cells = <1>;\n" "+\t\t};\n" "+\n" - "+\t\tclk_gates9: gate-clk@200000f4 {\n" + "+\t\tclk_gates9: gate-clk at 200000f4 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-gate-clk\";\n" "+\t\t\treg = <0x200000f4 0x4>;\n" "+\t\t\tclocks = <&dummy>, <&clk_gates0 5>,\n" @@ -545,7 +533,7 @@ "@@ -0,0 +1,131 @@\n" "+/*\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -682,7 +670,7 @@ "@@ -0,0 +1,19 @@\n" "+/*\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -707,7 +695,7 @@ "@@ -0,0 +1,330 @@\n" "+/*\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -1038,4 +1026,4 @@ "-- \n" 1.7.2.3 -bc60d47f7631389771c74fa663e3ad96ceb1e08ecbbc338c6133381e3c83cbf5 +be71573efccdfac2d80e410bdeb6351a8f564d52a533b6ab68fd6d9b1a8bd060
diff --git a/a/1.txt b/N2/1.txt index 78602f0..1934f3c 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -6,7 +6,7 @@ The plls are currently read-only, as their setting needs more investigation. This also results in slow cpu speeds, as the apll starts at a default of 600mhz. -Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> +Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/arm/boot/dts/rk3066a-clocks.dtsi | 467 +++++++++++++++++++++++++++++++ drivers/clk/Makefile | 1 + @@ -29,7 +29,7 @@ index 0000000..d797710 @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -526,7 +526,7 @@ index 0000000..4456445 @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -663,7 +663,7 @@ index 0000000..a63288a @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -688,7 +688,7 @@ index 0000000..660b00f @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> ++ * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by diff --git a/a/content_digest b/N2/content_digest index 6546e91..ec05c4b 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,20 +1,23 @@ "ref\0201306111328.52679.heiko@sntech.de\0" - "ref\0201306111328.52679.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org\0" - "From\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" + "From\0Heiko St\303\274bner <heiko@sntech.de>\0" "Subject\0[PATCH v3 5/7] clk: add basic Rockchip rk3066a clock support\0" "Date\0Tue, 11 Jun 2013 13:31:31 +0200\0" - "To\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" - "Cc\0Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>" - Seungwon Jeon <tgih.jun-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> - linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org> - Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> - Andy Shevchenko <andy.shevchenko-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> - Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> - Chris Ball <cjb-2X9k7bc8m7Mdnm+yROfE0A@public.gmane.org> - " devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" + Mike Turquette <mturquette@linaro.org> + Seungwon Jeon <tgih.jun@samsung.com> + Jaehoon Chung <jh80.chung@samsung.com> + Chris Ball <cjb@laptop.org> + linux-mmc@vger.kernel.org + Grant Likely <grant.likely@linaro.org> + Rob Herring <rob.herring@calxeda.com> + Linus Walleij <linus.walleij@linaro.org> + devicetree-discuss@lists.ozlabs.org + Russell King <linux@arm.linux.org.uk> + Arnd Bergmann <arnd@arndb.de> + Olof Johansson <olof@lixom.net> + Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + " Andy Shevchenko <andy.shevchenko@gmail.com>\0" "\00:1\0" "b\0" "This adds basic support for clocks on Rockchip rk3066 SoCs.\n" @@ -25,7 +28,7 @@ "investigation. This also results in slow cpu speeds, as the apll starts\n" "at a default of 600mhz.\n" "\n" - "Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "Signed-off-by: Heiko Stuebner <heiko@sntech.de>\n" "---\n" " arch/arm/boot/dts/rk3066a-clocks.dtsi | 467 +++++++++++++++++++++++++++++++\n" " drivers/clk/Makefile | 1 +\n" @@ -48,7 +51,7 @@ "@@ -0,0 +1,467 @@\n" "+/*\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -545,7 +548,7 @@ "@@ -0,0 +1,131 @@\n" "+/*\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -682,7 +685,7 @@ "@@ -0,0 +1,19 @@\n" "+/*\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -707,7 +710,7 @@ "@@ -0,0 +1,330 @@\n" "+/*\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" + "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -1038,4 +1041,4 @@ "-- \n" 1.7.2.3 -bc60d47f7631389771c74fa663e3ad96ceb1e08ecbbc338c6133381e3c83cbf5 +4944a742809154e63d5e3d0fc13193da490cb19a156d821b692ac8b8ddd25d2f
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.