diff for duplicates of <201306111332.46873.heiko@sntech.de> diff --git a/a/1.txt b/N1/1.txt index 71b6b8b..5f9ee1c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -80,13 +80,13 @@ index 0000000..afb73f2 + #address-cells = <1>; + #size-cells = <0>; + -+ cpu@0 { ++ cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; -+ cpu@1 { ++ cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; @@ -100,7 +100,7 @@ index 0000000..afb73f2 + compatible = "simple-bus"; + ranges; + -+ gic: interrupt-controller@1013d000 { ++ gic: interrupt-controller at 1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; @@ -108,21 +108,21 @@ index 0000000..afb73f2 + <0x1013c100 0x0100>; + }; + -+ L2: l2-cache-controller@10138000 { ++ L2: l2-cache-controller at 10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + -+ local-timer@1013c600 { ++ local-timer at 1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = <GIC_PPI 13 0x304>; + clocks = <&div_core_periph>; + }; + -+ timer@20038000 { ++ timer at 20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -130,7 +130,7 @@ index 0000000..afb73f2 + clock-names = "timer", "pclk"; + }; + -+ timer@2003a000 { ++ timer at 2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -138,7 +138,7 @@ index 0000000..afb73f2 + clock-names = "timer", "pclk"; + }; + -+ timer@2000e000 { ++ timer at 2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; @@ -146,14 +146,14 @@ index 0000000..afb73f2 + clock-names = "timer", "pclk"; + }; + -+ pinctrl@20008000 { ++ pinctrl at 20008000 { + compatible = "rockchip,rk3066a-pinctrl"; + reg = <0x20008000 0x150>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + -+ gpio0: gpio0@20034000 { ++ gpio0: gpio0 at 20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; @@ -166,7 +166,7 @@ index 0000000..afb73f2 + #interrupt-cells = <2>; + }; + -+ gpio1: gpio1@2003c000 { ++ gpio1: gpio1 at 2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -179,7 +179,7 @@ index 0000000..afb73f2 + #interrupt-cells = <2>; + }; + -+ gpio2: gpio2@2003e000 { ++ gpio2: gpio2 at 2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -192,7 +192,7 @@ index 0000000..afb73f2 + #interrupt-cells = <2>; + }; + -+ gpio3: gpio3@20080000 { ++ gpio3: gpio3 at 20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -205,7 +205,7 @@ index 0000000..afb73f2 + #interrupt-cells = <2>; + }; + -+ gpio4: gpio4@20084000 { ++ gpio4: gpio4 at 20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; @@ -218,7 +218,7 @@ index 0000000..afb73f2 + #interrupt-cells = <2>; + }; + -+ gpio6: gpio6@2000a000 { ++ gpio6: gpio6 at 2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; @@ -373,7 +373,7 @@ index 0000000..afb73f2 + }; + }; + -+ uart0: serial@10124000 { ++ uart0: serial at 10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; @@ -383,7 +383,7 @@ index 0000000..afb73f2 + status = "disabled"; + }; + -+ uart1: serial@10126000 { ++ uart1: serial at 10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -393,7 +393,7 @@ index 0000000..afb73f2 + status = "disabled"; + }; + -+ uart2: serial@20064000 { ++ uart2: serial at 20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -403,7 +403,7 @@ index 0000000..afb73f2 + status = "disabled"; + }; + -+ uart3: serial@20068000 { ++ uart3: serial at 20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -413,7 +413,7 @@ index 0000000..afb73f2 + status = "disabled"; + }; + -+ dwmmc@10214000 { ++ dwmmc at 10214000 { + compatible = "rockchip,cortex-a9-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -426,7 +426,7 @@ index 0000000..afb73f2 + status = "disabled"; + }; + -+ dwmmc@10218000 { ++ dwmmc at 10218000 { + compatible = "rockchip,cortex-a9-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N1/content_digest index 7a92e52..f869275 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,23 +1,8 @@ "ref\0201306111328.52679.heiko@sntech.de\0" - "From\0Heiko St\303\274bner <heiko@sntech.de>\0" + "From\0heiko@sntech.de (Heiko St\303\274bner)\0" "Subject\0[PATCH v3 7/7] arm: add basic support for Rockchip RK3066a boards\0" "Date\0Tue, 11 Jun 2013 13:32:46 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" - "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>" - Mike Turquette <mturquette@linaro.org> - Seungwon Jeon <tgih.jun@samsung.com> - Jaehoon Chung <jh80.chung@samsung.com> - Chris Ball <cjb@laptop.org> - linux-mmc@vger.kernel.org - Grant Likely <grant.likely@linaro.org> - Rob Herring <rob.herring@calxeda.com> - Linus Walleij <linus.walleij@linaro.org> - devicetree-discuss@lists.ozlabs.org - Russell King <linux@arm.linux.org.uk> - Arnd Bergmann <arnd@arndb.de> - Olof Johansson <olof@lixom.net> - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - " Andy Shevchenko <andy.shevchenko@gmail.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "This adds a generic devicetree board file and a dtsi for boards\n" @@ -102,13 +87,13 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu@0 {\n" + "+\t\tcpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a9\";\n" "+\t\t\tnext-level-cache = <&L2>;\n" "+\t\t\treg = <0x0>;\n" "+\t\t};\n" - "+\t\tcpu@1 {\n" + "+\t\tcpu at 1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a9\";\n" "+\t\t\tnext-level-cache = <&L2>;\n" @@ -122,7 +107,7 @@ "+\t\tcompatible = \"simple-bus\";\n" "+\t\tranges;\n" "+\n" - "+\t\tgic: interrupt-controller@1013d000 {\n" + "+\t\tgic: interrupt-controller at 1013d000 {\n" "+\t\t\tcompatible = \"arm,cortex-a9-gic\";\n" "+\t\t\tinterrupt-controller;\n" "+\t\t\t#interrupt-cells = <3>;\n" @@ -130,21 +115,21 @@ "+\t\t\t <0x1013c100 0x0100>;\n" "+\t\t};\n" "+\n" - "+\t\tL2: l2-cache-controller@10138000 {\n" + "+\t\tL2: l2-cache-controller at 10138000 {\n" "+\t\t\tcompatible = \"arm,pl310-cache\";\n" "+\t\t\treg = <0x10138000 0x1000>;\n" "+\t\t\tcache-unified;\n" "+\t\t\tcache-level = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tlocal-timer@1013c600 {\n" + "+\t\tlocal-timer at 1013c600 {\n" "+\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n" "+\t\t\treg = <0x1013c600 0x20>;\n" "+\t\t\tinterrupts = <GIC_PPI 13 0x304>;\n" "+\t\t\tclocks = <&div_core_periph>;\n" "+\t\t};\n" "+\n" - "+\t\ttimer@20038000 {\n" + "+\t\ttimer at 20038000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-timer-osc\";\n" "+\t\t\treg = <0x20038000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -152,7 +137,7 @@ "+\t\t\tclock-names = \"timer\", \"pclk\";\n" "+\t\t};\n" "+\n" - "+\t\ttimer@2003a000 {\n" + "+\t\ttimer at 2003a000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-timer-osc\";\n" "+\t\t\treg = <0x2003a000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -160,7 +145,7 @@ "+\t\t\tclock-names = \"timer\", \"pclk\";\n" "+\t\t};\n" "+\n" - "+\t\ttimer@2000e000 {\n" + "+\t\ttimer at 2000e000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-timer-osc\";\n" "+\t\t\treg = <0x2000e000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -168,14 +153,14 @@ "+\t\t\tclock-names = \"timer\", \"pclk\";\n" "+\t\t};\n" "+\n" - "+\t\tpinctrl@20008000 {\n" + "+\t\tpinctrl at 20008000 {\n" "+\t\t\tcompatible = \"rockchip,rk3066a-pinctrl\";\n" "+\t\t\treg = <0x20008000 0x150>;\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges;\n" "+\n" - "+\t\t\tgpio0: gpio0@20034000 {\n" + "+\t\t\tgpio0: gpio0 at 20034000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x20034000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -188,7 +173,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio1: gpio1@2003c000 {\n" + "+\t\t\tgpio1: gpio1 at 2003c000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x2003c000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -201,7 +186,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio2: gpio2@2003e000 {\n" + "+\t\t\tgpio2: gpio2 at 2003e000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x2003e000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -214,7 +199,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio3: gpio3@20080000 {\n" + "+\t\t\tgpio3: gpio3 at 20080000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x20080000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -227,7 +212,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio4: gpio4@20084000 {\n" + "+\t\t\tgpio4: gpio4 at 20084000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x20084000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -240,7 +225,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio6: gpio6@2000a000 {\n" + "+\t\t\tgpio6: gpio6 at 2000a000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x2000a000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -395,7 +380,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tuart0: serial@10124000 {\n" + "+\t\tuart0: serial at 10124000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0x10124000 0x400>;\n" "+\t\t\tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -405,7 +390,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart1: serial@10126000 {\n" + "+\t\tuart1: serial at 10126000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0x10126000 0x400>;\n" "+\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -415,7 +400,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart2: serial@20064000 {\n" + "+\t\tuart2: serial at 20064000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0x20064000 0x400>;\n" "+\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -425,7 +410,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart3: serial@20068000 {\n" + "+\t\tuart3: serial at 20068000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0x20068000 0x400>;\n" "+\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -435,7 +420,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tdwmmc@10214000 {\n" + "+\t\tdwmmc at 10214000 {\n" "+\t\t\tcompatible = \"rockchip,cortex-a9-dw-mshc\";\n" "+\t\t\treg = <0x10214000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -448,7 +433,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tdwmmc@10218000 {\n" + "+\t\tdwmmc at 10218000 {\n" "+\t\t\tcompatible = \"rockchip,cortex-a9-dw-mshc\";\n" "+\t\t\treg = <0x10218000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -554,4 +539,4 @@ "-- \n" 1.7.2.3 -516ca8cc6a201814ab1617c08e6d1db05ccec2c3ebea5e2b7be91fa8aeb48db9 +53c3bb68a91787330b71d02c248fa112523ae7522ad96188bbbb1ea97ddd0312
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