From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 4/9] drm/i915: fixup g4x pll limits Date: Wed, 12 Jun 2013 10:38:55 +0300 Message-ID: <20130612073855.GN5004@intel.com> References: <1369166099-1840-1-git-send-email-daniel.vetter@ffwll.ch> <1369166099-1840-5-git-send-email-daniel.vetter@ffwll.ch> <20130611230739.GB11691@strange.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id A438CE6066 for ; Wed, 12 Jun 2013 00:38:59 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130611230739.GB11691@strange.amr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Damien Lespiau Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Wed, Jun 12, 2013 at 12:07:39AM +0100, Damien Lespiau wrote: > On Tue, May 21, 2013 at 09:54:54PM +0200, Daniel Vetter wrote: > > Again the same confusion that our code expects m1/m2 in register values. > > This time around with the added fun that many of the existing values > > have been all off by a bit in different directions. Hence extract a > > common #define. > > = > > Note that n limits differ between lvds and other outputs. Strangely the= y've > > all been correct already. > > = > > v2: Rebased on top of the DP pll rework, which makes it even more > > obvious that we can do this ... > = > I'm a bit confused by this one: > = > - I don't seem to find the special LVDS limits for n Me neither. > - Those limits are gated by a IS_G4X(). IS_G4X() is true for eaglelake > and cantiga. The docs single out Cantiga and we seem to need a > different set of limits for that platform (compared to the rest of > gen4) platforms? I've noticed that the docs often mention just CTG leaving out ELK, even though the stuff it's describing applies to both. > - The limits for n are 3-6 or 3-5 in this code but I read 3-8 and 5-6 > (cantiga) I see 3-8 and 4-6. > - m doesn't seem to match what I have, it seems like it could be the > cantiga values (except that m is in "formula space" so we don't > substract 2) 105-140 is what the spec tells me, so a bit off either way. There's more inconsistency w/ the p/p1 limits too, and the single channel lvds dotclock limit doesn't agree w/ the spec either. > - m1 and m2 seem to match what I have for cantiga, are we supposed to > have those limits for eaglelake as well? > = > Well, the only conclusion is that I must be reading the wrong docs, or? > = > > = > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/intel_display.c | 20 ++++++++------------ > > 1 file changed, 8 insertions(+), 12 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index ea8eb0c..cb54131 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -136,14 +136,16 @@ static const intel_limit_t intel_limits_i9xx_lvds= =3D { > > .p2_slow =3D 14, .p2_fast =3D 7 }, > > }; > > = > > +#define G4X_DPLL_M_LIMITS \ > > + .m =3D { .min =3D 104, .max =3D 138 },\ > > + .m1 =3D { .min =3D 15, .max =3D 21 },\ > > + .m2 =3D { .min =3D 3, .max =3D 11 }, > > = > > static const intel_limit_t intel_limits_g4x_sdvo =3D { > > .dot =3D { .min =3D 25000, .max =3D 270000 }, > > .vco =3D { .min =3D 1750000, .max =3D 3500000}, > > .n =3D { .min =3D 1, .max =3D 4 }, > > - .m =3D { .min =3D 104, .max =3D 138 }, > > - .m1 =3D { .min =3D 17, .max =3D 23 }, > > - .m2 =3D { .min =3D 5, .max =3D 11 }, > > + G4X_DPLL_M_LIMITS > > .p =3D { .min =3D 10, .max =3D 30 }, > > .p1 =3D { .min =3D 1, .max =3D 3}, > > .p2 =3D { .dot_limit =3D 270000, > > @@ -156,9 +158,7 @@ static const intel_limit_t intel_limits_g4x_hdmi = =3D { > > .dot =3D { .min =3D 22000, .max =3D 400000 }, > > .vco =3D { .min =3D 1750000, .max =3D 3500000}, > > .n =3D { .min =3D 1, .max =3D 4 }, > > - .m =3D { .min =3D 104, .max =3D 138 }, > > - .m1 =3D { .min =3D 16, .max =3D 23 }, > > - .m2 =3D { .min =3D 5, .max =3D 11 }, > > + G4X_DPLL_M_LIMITS > > .p =3D { .min =3D 5, .max =3D 80 }, > > .p1 =3D { .min =3D 1, .max =3D 8}, > > .p2 =3D { .dot_limit =3D 165000, > > @@ -169,9 +169,7 @@ static const intel_limit_t intel_limits_g4x_single_= channel_lvds =3D { > > .dot =3D { .min =3D 20000, .max =3D 115000 }, > > .vco =3D { .min =3D 1750000, .max =3D 3500000 }, > > .n =3D { .min =3D 1, .max =3D 3 }, > > - .m =3D { .min =3D 104, .max =3D 138 }, > > - .m1 =3D { .min =3D 17, .max =3D 23 }, > > - .m2 =3D { .min =3D 5, .max =3D 11 }, > > + G4X_DPLL_M_LIMITS > > .p =3D { .min =3D 28, .max =3D 112 }, > > .p1 =3D { .min =3D 2, .max =3D 8 }, > > .p2 =3D { .dot_limit =3D 0, > > @@ -183,9 +181,7 @@ static const intel_limit_t intel_limits_g4x_dual_ch= annel_lvds =3D { > > .dot =3D { .min =3D 80000, .max =3D 224000 }, > > .vco =3D { .min =3D 1750000, .max =3D 3500000 }, > > .n =3D { .min =3D 1, .max =3D 3 }, > > - .m =3D { .min =3D 104, .max =3D 138 }, > > - .m1 =3D { .min =3D 17, .max =3D 23 }, > > - .m2 =3D { .min =3D 5, .max =3D 11 }, > > + G4X_DPLL_M_LIMITS > > .p =3D { .min =3D 14, .max =3D 42 }, > > .p1 =3D { .min =3D 2, .max =3D 6 }, > > .p2 =3D { .dot_limit =3D 0, > > -- = > > 1.7.11.7 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC