From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 5/9] drm/i915: pnv dpll doesn't use m1! Date: Wed, 12 Jun 2013 21:28:45 +0200 Message-ID: <20130612192845.GG22870@phenom.ffwll.local> References: <1369166099-1840-1-git-send-email-daniel.vetter@ffwll.ch> <1369166099-1840-6-git-send-email-daniel.vetter@ffwll.ch> <20130611233840.GC11691@strange.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f45.google.com (mail-ee0-f45.google.com [74.125.83.45]) by gabe.freedesktop.org (Postfix) with ESMTP id BF083E5C5B for ; Wed, 12 Jun 2013 12:28:50 -0700 (PDT) Received: by mail-ee0-f45.google.com with SMTP id c1so4308919eek.18 for ; Wed, 12 Jun 2013 12:28:50 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130611233840.GC11691@strange.amr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Damien Lespiau Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Wed, Jun 12, 2013 at 12:38:40AM +0100, Damien Lespiau wrote: > On Tue, May 21, 2013 at 09:54:55PM +0200, Daniel Vetter wrote: > > So don't try to store it in the DPLL_FP register. > > > > Otherwise it looks like the limits for pineview are correct: It has > > it's own clock computation code, which doesn't use an offset for n > > divisors, and the register value based m limits look sane enough. > > - n can vary between 2 and 6, but we declare the 3-6 as limits. > - p1 seems to be able to go up to 9 > - the m upper limit seems a bit big, but the docs are a bit shy on > that values for pnv. > > Otherwise, the change itself seems good: Quoted in the commit message and merged the patch. > Reviewed-by: Damien Lespiau Thanks for the review, Daniel > > > > > v2: Rebase on top of the pineview clock refactor and fixup up the > > commit message: It's m1 pnv doens't care about, not m2! > > > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index cb54131..520e340 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -4300,7 +4300,7 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) > > > > static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) > > { > > - return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2; > > + return (1 << dpll->n) << 16 | dpll->m2; > > } > > > > static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) > > -- > > 1.7.11.7 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch