diff for duplicates of <201306131702.13400.heiko@sntech.de> diff --git a/a/1.txt b/N1/1.txt index b21e628..fc8d931 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,7 +5,7 @@ Apart from the generic parts (gic, clocks, pinctrl) the only components currently supported are the timers, uarts and mmc ports (all DesignWare- based). -Signed-off-by: Heiko Stuebner <heiko@sntech.de> +Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> --- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + @@ -52,7 +52,7 @@ index 0000000..56bfac9 @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko@sntech.de> ++ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -80,13 +80,13 @@ index 0000000..56bfac9 + #address-cells = <1>; + #size-cells = <0>; + -+ cpu at 0 { ++ cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; -+ cpu at 1 { ++ cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; @@ -100,7 +100,7 @@ index 0000000..56bfac9 + compatible = "simple-bus"; + ranges; + -+ gic: interrupt-controller at 1013d000 { ++ gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; @@ -108,21 +108,21 @@ index 0000000..56bfac9 + <0x1013c100 0x0100>; + }; + -+ L2: l2-cache-controller at 10138000 { ++ L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + -+ local-timer at 1013c600 { ++ local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = <GIC_PPI 13 0x304>; + clocks = <&dummy150m>; + }; + -+ timer at 20038000 { ++ timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -130,7 +130,7 @@ index 0000000..56bfac9 + clock-names = "timer", "pclk"; + }; + -+ timer at 2003a000 { ++ timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -138,7 +138,7 @@ index 0000000..56bfac9 + clock-names = "timer", "pclk"; + }; + -+ timer at 2000e000 { ++ timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; @@ -146,14 +146,14 @@ index 0000000..56bfac9 + clock-names = "timer", "pclk"; + }; + -+ pinctrl at 20008000 { ++ pinctrl@20008000 { + compatible = "rockchip,rk3066a-pinctrl"; + reg = <0x20008000 0x150>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + -+ gpio0: gpio0 at 20034000 { ++ gpio0: gpio0@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; @@ -166,7 +166,7 @@ index 0000000..56bfac9 + #interrupt-cells = <2>; + }; + -+ gpio1: gpio1 at 2003c000 { ++ gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -179,7 +179,7 @@ index 0000000..56bfac9 + #interrupt-cells = <2>; + }; + -+ gpio2: gpio2 at 2003e000 { ++ gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -192,7 +192,7 @@ index 0000000..56bfac9 + #interrupt-cells = <2>; + }; + -+ gpio3: gpio3 at 20080000 { ++ gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -205,7 +205,7 @@ index 0000000..56bfac9 + #interrupt-cells = <2>; + }; + -+ gpio4: gpio4 at 20084000 { ++ gpio4: gpio4@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; @@ -218,7 +218,7 @@ index 0000000..56bfac9 + #interrupt-cells = <2>; + }; + -+ gpio6: gpio6 at 2000a000 { ++ gpio6: gpio6@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; @@ -373,7 +373,7 @@ index 0000000..56bfac9 + }; + }; + -+ uart0: serial at 10124000 { ++ uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; @@ -383,7 +383,7 @@ index 0000000..56bfac9 + status = "disabled"; + }; + -+ uart1: serial at 10126000 { ++ uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -393,7 +393,7 @@ index 0000000..56bfac9 + status = "disabled"; + }; + -+ uart2: serial at 20064000 { ++ uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -403,7 +403,7 @@ index 0000000..56bfac9 + status = "disabled"; + }; + -+ uart3: serial at 20068000 { ++ uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -413,7 +413,7 @@ index 0000000..56bfac9 + status = "disabled"; + }; + -+ dwmmc at 10214000 { ++ dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -426,7 +426,7 @@ index 0000000..56bfac9 + status = "disabled"; + }; + -+ dwmmc at 10218000 { ++ dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; @@ -479,7 +479,7 @@ index 0000000..0933e17 + * Device Tree support for Rockchip SoCs + * + * Copyright (c) 2013 MundoReader S.L. -+ * Author: Heiko Stuebner <heiko@sntech.de> ++ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by diff --git a/a/content_digest b/N1/content_digest index fd5d940..a7df1ae 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,13 @@ "ref\0201306131658.36584.heiko@sntech.de\0" - "From\0heiko@sntech.de (Heiko St\303\274bner)\0" + "ref\0201306131658.36584.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org\0" + "From\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" "Subject\0[PATCH v4 4/4] arm: add basic support for Rockchip RK3066a boards\0" "Date\0Thu, 13 Jun 2013 17:02:13 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" + "Cc\0Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>" + devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org + Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org> + " Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" "\00:1\0" "b\0" "This adds a generic devicetree board file and a dtsi for boards\n" @@ -12,7 +17,7 @@ "currently supported are the timers, uarts and mmc ports (all DesignWare-\n" "based).\n" "\n" - "Signed-off-by: Heiko Stuebner <heiko@sntech.de>\n" + "Signed-off-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" "---\n" " arch/arm/Kconfig | 2 +\n" " arch/arm/Makefile | 1 +\n" @@ -59,7 +64,7 @@ "@@ -0,0 +1,390 @@\n" "+/*\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" + "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -87,13 +92,13 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu at 0 {\n" + "+\t\tcpu@0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a9\";\n" "+\t\t\tnext-level-cache = <&L2>;\n" "+\t\t\treg = <0x0>;\n" "+\t\t};\n" - "+\t\tcpu at 1 {\n" + "+\t\tcpu@1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a9\";\n" "+\t\t\tnext-level-cache = <&L2>;\n" @@ -107,7 +112,7 @@ "+\t\tcompatible = \"simple-bus\";\n" "+\t\tranges;\n" "+\n" - "+\t\tgic: interrupt-controller at 1013d000 {\n" + "+\t\tgic: interrupt-controller@1013d000 {\n" "+\t\t\tcompatible = \"arm,cortex-a9-gic\";\n" "+\t\t\tinterrupt-controller;\n" "+\t\t\t#interrupt-cells = <3>;\n" @@ -115,21 +120,21 @@ "+\t\t\t <0x1013c100 0x0100>;\n" "+\t\t};\n" "+\n" - "+\t\tL2: l2-cache-controller at 10138000 {\n" + "+\t\tL2: l2-cache-controller@10138000 {\n" "+\t\t\tcompatible = \"arm,pl310-cache\";\n" "+\t\t\treg = <0x10138000 0x1000>;\n" "+\t\t\tcache-unified;\n" "+\t\t\tcache-level = <2>;\n" "+\t\t};\n" "+\n" - "+\t\tlocal-timer at 1013c600 {\n" + "+\t\tlocal-timer@1013c600 {\n" "+\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n" "+\t\t\treg = <0x1013c600 0x20>;\n" "+\t\t\tinterrupts = <GIC_PPI 13 0x304>;\n" "+\t\t\tclocks = <&dummy150m>;\n" "+\t\t};\n" "+\n" - "+\t\ttimer at 20038000 {\n" + "+\t\ttimer@20038000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-timer-osc\";\n" "+\t\t\treg = <0x20038000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -137,7 +142,7 @@ "+\t\t\tclock-names = \"timer\", \"pclk\";\n" "+\t\t};\n" "+\n" - "+\t\ttimer at 2003a000 {\n" + "+\t\ttimer@2003a000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-timer-osc\";\n" "+\t\t\treg = <0x2003a000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -145,7 +150,7 @@ "+\t\t\tclock-names = \"timer\", \"pclk\";\n" "+\t\t};\n" "+\n" - "+\t\ttimer at 2000e000 {\n" + "+\t\ttimer@2000e000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-timer-osc\";\n" "+\t\t\treg = <0x2000e000 0x100>;\n" "+\t\t\tinterrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -153,14 +158,14 @@ "+\t\t\tclock-names = \"timer\", \"pclk\";\n" "+\t\t};\n" "+\n" - "+\t\tpinctrl at 20008000 {\n" + "+\t\tpinctrl@20008000 {\n" "+\t\t\tcompatible = \"rockchip,rk3066a-pinctrl\";\n" "+\t\t\treg = <0x20008000 0x150>;\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges;\n" "+\n" - "+\t\t\tgpio0: gpio0 at 20034000 {\n" + "+\t\t\tgpio0: gpio0@20034000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x20034000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -173,7 +178,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio1: gpio1 at 2003c000 {\n" + "+\t\t\tgpio1: gpio1@2003c000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x2003c000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -186,7 +191,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio2: gpio2 at 2003e000 {\n" + "+\t\t\tgpio2: gpio2@2003e000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x2003e000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -199,7 +204,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio3: gpio3 at 20080000 {\n" + "+\t\t\tgpio3: gpio3@20080000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x20080000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -212,7 +217,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio4: gpio4 at 20084000 {\n" + "+\t\t\tgpio4: gpio4@20084000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x20084000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -225,7 +230,7 @@ "+\t\t\t\t#interrupt-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio6: gpio6 at 2000a000 {\n" + "+\t\t\tgpio6: gpio6@2000a000 {\n" "+\t\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "+\t\t\t\treg = <0x2000a000 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -380,7 +385,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tuart0: serial at 10124000 {\n" + "+\t\tuart0: serial@10124000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0x10124000 0x400>;\n" "+\t\t\tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -390,7 +395,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart1: serial at 10126000 {\n" + "+\t\tuart1: serial@10126000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0x10126000 0x400>;\n" "+\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -400,7 +405,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart2: serial at 20064000 {\n" + "+\t\tuart2: serial@20064000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0x20064000 0x400>;\n" "+\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -410,7 +415,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tuart3: serial at 20068000 {\n" + "+\t\tuart3: serial@20068000 {\n" "+\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\treg = <0x20068000 0x400>;\n" "+\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -420,7 +425,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tdwmmc at 10214000 {\n" + "+\t\tdwmmc@10214000 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-dw-mshc\";\n" "+\t\t\treg = <0x10214000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -433,7 +438,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tdwmmc at 10218000 {\n" + "+\t\tdwmmc@10218000 {\n" "+\t\t\tcompatible = \"rockchip,rk2928-dw-mshc\";\n" "+\t\t\treg = <0x10218000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -486,7 +491,7 @@ "+ * Device Tree support for Rockchip SoCs\n" "+ *\n" "+ * Copyright (c) 2013 MundoReader S.L.\n" - "+ * Author: Heiko Stuebner <heiko@sntech.de>\n" + "+ * Author: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\n" "+ *\n" "+ * This program is free software; you can redistribute it and/or modify\n" "+ * it under the terms of the GNU General Public License as published by\n" @@ -539,4 +544,4 @@ "-- \n" 1.7.10.4 -d70a592340092a782f0c608ef03c5a2469f9faef4c24462ef8086fd94b9e68f4 +c5a181c6bf6836b283107d3f3fabf0c2c9a9ae44c1490520aa885753440c4c7b
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