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Date:   Tue, 18 Jun 2013 16:42:53 +0200
From:   Ralf Baechle <ralf@linux-mips.org>
To:     Paul Burton <paul.burton@imgtec.com>
Cc:     linux-mips@linux-mips.org, Chris Dearman <chris.dearman@imgtec.com>
Subject: Re: [PATCH] mips: fix execution hazard during watchpoint register
 probe
Message-ID: <20130618144253.GA19573@linux-mips.org>
References: <1371314080-48198-1-git-send-email-paul.burton@imgtec.com>
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On Sat, Jun 15, 2013 at 05:34:40PM +0100, Paul Burton wrote:

> Writing a value to a WatchLo* register creates an execution hazard, so
> if its value is then read before that hazard is cleared then said value
> may be invalid. The mips_probe_watch_registers function must therefore
> clear the execution hazard between setting the match bits in a WatchLo*
> register & reading the register back in order to check which are set.
> 
> This fixes intermittent incorrect watchpoint register probing on some
> MIPS cores such as interAptiv & proAptiv.

Obviously correct.  Did somebody once have a tool to test for this kind
of back-to-back cp0 issues?

  Ralf