diff for duplicates of <20130620232903.9136.70323@quantum> diff --git a/a/1.txt b/N1/1.txt index 5f8f770..c6d2815 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,4 +1,4 @@ -Quoting Heiko St?bner (2013-06-13 07:59:40) +Quoting Heiko Stübner (2013-06-13 07:59:40) > This adds basic support for gate-clocks on Rockchip SoCs. > There are 16 gates in each register and use the HIWORD_MASK > mechanism for changing gate settings. @@ -59,7 +59,7 @@ Mike > + > +Example using multiple gate clocks: > + -> + clk_gates0: gate-clk at 200000d0 { +> + clk_gates0: gate-clk@200000d0 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000d0 0x4>; > + clocks = <&dummy>, <&dummy>, @@ -84,7 +84,7 @@ Mike > + #clock-cells = <1>; > + }; > + -> + clk_gates1: gate-clk at 200000d4 { +> + clk_gates1: gate-clk@200000d4 { > + compatible = "rockchip,rk2928-gate-clk"; > + reg = <0x200000d4 0x4>; > + clocks = <&xin24m>, <&xin24m>, @@ -233,3 +233,7 @@ Mike > +CLK_OF_DECLARE(rk2928_gate, "rockchip,rk2928-gate-clk", rk2928_gate_clk_init); > -- > 1.7.10.4 +_______________________________________________ +devicetree-discuss mailing list +devicetree-discuss@lists.ozlabs.org +https://lists.ozlabs.org/listinfo/devicetree-discuss diff --git a/a/content_digest b/N1/content_digest index ef27682..13b192d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,12 +1,17 @@ "ref\0201306131658.36584.heiko@sntech.de\0" "ref\0201306131659.40802.heiko@sntech.de\0" - "From\0mturquette@linaro.org (Mike Turquette)\0" - "Subject\0[PATCH v4 1/4] clk: add support for Rockchip gate clocks\0" + "ref\0201306131659.40802.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org\0" + "From\0Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Subject\0Re: [PATCH v4 1/4] clk: add support for Rockchip gate clocks\0" "Date\0Thu, 20 Jun 2013 16:29:03 -0700\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>" + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" + "Cc\0Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>" + devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org + " Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>\0" "\00:1\0" "b\0" - "Quoting Heiko St?bner (2013-06-13 07:59:40)\n" + "Quoting Heiko St\303\274bner (2013-06-13 07:59:40)\n" "> This adds basic support for gate-clocks on Rockchip SoCs.\n" "> There are 16 gates in each register and use the HIWORD_MASK\n" "> mechanism for changing gate settings.\n" @@ -67,7 +72,7 @@ "> +\n" "> +Example using multiple gate clocks:\n" "> +\n" - "> + clk_gates0: gate-clk at 200000d0 {\n" + "> + clk_gates0: gate-clk@200000d0 {\n" "> + compatible = \"rockchip,rk2928-gate-clk\";\n" "> + reg = <0x200000d0 0x4>;\n" "> + clocks = <&dummy>, <&dummy>,\n" @@ -92,7 +97,7 @@ "> + #clock-cells = <1>;\n" "> + };\n" "> +\n" - "> + clk_gates1: gate-clk at 200000d4 {\n" + "> + clk_gates1: gate-clk@200000d4 {\n" "> + compatible = \"rockchip,rk2928-gate-clk\";\n" "> + reg = <0x200000d4 0x4>;\n" "> + clocks = <&xin24m>, <&xin24m>,\n" @@ -240,6 +245,10 @@ "> +}\n" "> +CLK_OF_DECLARE(rk2928_gate, \"rockchip,rk2928-gate-clk\", rk2928_gate_clk_init);\n" "> -- \n" - > 1.7.10.4 + "> 1.7.10.4\n" + "_______________________________________________\n" + "devicetree-discuss mailing list\n" + "devicetree-discuss@lists.ozlabs.org\n" + https://lists.ozlabs.org/listinfo/devicetree-discuss -f8abdecacd1750aa10a5cfc551e65f8968e909d1b6c0d88e2bc12b355cfd2c65 +105278b8b1e503a7ef6213788b0f53c3571bdc1f9dd39e5d5a554fc004b5363b
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