diff for duplicates of <20130621012200.9136.89246@quantum>

diff --git a/a/1.txt b/N1/1.txt
index 082b884..eba11cd 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,4 +1,4 @@
-Quoting Heiko St?bner (2013-06-20 16:30:32)
+Quoting Heiko Stübner (2013-06-20 16:30:32)
 > This adds a basic clock setup for rk3066a SoCs. Only the gates are
 > set up currently, as the mux and dividers should use the upcoming
 > generic devicetree bindings.
@@ -81,7 +81,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <0>;
 > +               };
 > +
-> +               clk_gates0: gate-clk at 200000d0 {
+> +               clk_gates0: gate-clk@200000d0 {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000d0 0x4>;
 > +                       clocks = <&dummy>, <&dummy>,
@@ -106,7 +106,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <1>;
 > +               };
 > +
-> +               clk_gates1: gate-clk at 200000d4 {
+> +               clk_gates1: gate-clk@200000d4 {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000d4 0x4>;
 > +                       clocks = <&xin24m>, <&xin24m>,
@@ -131,7 +131,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <1>;
 > +               };
 > +
-> +               clk_gates2: gate-clk at 200000d8 {
+> +               clk_gates2: gate-clk@200000d8 {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000d8 0x4>;
 > +                       clocks = <&clk_gates2 1>, <&dummy>,
@@ -156,7 +156,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <1>;
 > +               };
 > +
-> +               clk_gates3: gate-clk at 200000dc {
+> +               clk_gates3: gate-clk@200000dc {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000dc 0x4>;
 > +                       clocks = <&dummy>, <&dummy>,
@@ -181,7 +181,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <1>;
 > +               };
 > +
-> +               clk_gates4: gate-clk at 200000e0 {
+> +               clk_gates4: gate-clk@200000e0 {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000e0 0x4>;
 > +                       clocks = <&clk_gates2 2>, <&clk_gates2 3>,
@@ -206,7 +206,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <1>;
 > +               };
 > +
-> +               clk_gates5: gate-clk at 200000e4 {
+> +               clk_gates5: gate-clk@200000e4 {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000e4 0x4>;
 > +                       clocks = <&clk_gates0 3>, <&clk_gates2 1>,
@@ -231,7 +231,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <1>;
 > +               };
 > +
-> +               clk_gates6: gate-clk at 200000e8 {
+> +               clk_gates6: gate-clk@200000e8 {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000e8 0x4>;
 > +                       clocks = <&clk_gates3 0>, <&clk_gates0 4>,
@@ -256,7 +256,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <1>;
 > +               };
 > +
-> +               clk_gates7: gate-clk at 200000ec {
+> +               clk_gates7: gate-clk@200000ec {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000ec 0x4>;
 > +                       clocks = <&clk_gates2 2>, <&clk_gates0 4>,
@@ -281,7 +281,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <1>;
 > +               };
 > +
-> +               clk_gates8: gate-clk at 200000f0 {
+> +               clk_gates8: gate-clk@200000f0 {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000f0 0x4>;
 > +                       clocks = <&clk_gates0 5>, <&clk_gates0 5>,
@@ -306,7 +306,7 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > +                       #clock-cells = <1>;
 > +               };
 > +
-> +               clk_gates9: gate-clk at 200000f4 {
+> +               clk_gates9: gate-clk@200000f4 {
 > +                       compatible = "rockchip,rk2928-gate-clk";
 > +                       reg = <0x200000f4 0x4>;
 > +                       clocks = <&dummy>, <&clk_gates0 5>,
@@ -335,5 +335,9 @@ Reviewed-by: Mike Turquette <mturquette@linaro.org>
 > 
 > _______________________________________________
 > linux-arm-kernel mailing list
-> linux-arm-kernel at lists.infradead.org
+> linux-arm-kernel@lists.infradead.org
 > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
+_______________________________________________
+devicetree-discuss mailing list
+devicetree-discuss@lists.ozlabs.org
+https://lists.ozlabs.org/listinfo/devicetree-discuss
diff --git a/a/content_digest b/N1/content_digest
index eff2e76..dc03ff6 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,12 +1,18 @@
  "ref\0201306210129.54629.heiko@sntech.de\0"
  "ref\0201306210130.33033.heiko@sntech.de\0"
- "From\0mturquette@linaro.org (Mike Turquette)\0"
- "Subject\0[PATCH v6 1/3] arm: Add basic clocks for Rockchip rk3066a SoCs\0"
+ "ref\0201306210130.33033.heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org\0"
+ "From\0Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0"
+ "Subject\0Re: [PATCH v6 1/3] arm: Add basic clocks for Rockchip rk3066a SoCs\0"
  "Date\0Thu, 20 Jun 2013 18:22:00 -0700\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>"
+ " Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>\0"
+ "Cc\0Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>"
+  devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
+  Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
+ " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0"
  "\00:1\0"
  "b\0"
- "Quoting Heiko St?bner (2013-06-20 16:30:32)\n"
+ "Quoting Heiko St\303\274bner (2013-06-20 16:30:32)\n"
  "> This adds a basic clock setup for rk3066a SoCs. Only the gates are\n"
  "> set up currently, as the mux and dividers should use the upcoming\n"
  "> generic devicetree bindings.\n"
@@ -89,7 +95,7 @@
  "> +                       #clock-cells = <0>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates0: gate-clk at 200000d0 {\n"
+ "> +               clk_gates0: gate-clk@200000d0 {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000d0 0x4>;\n"
  "> +                       clocks = <&dummy>, <&dummy>,\n"
@@ -114,7 +120,7 @@
  "> +                       #clock-cells = <1>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates1: gate-clk at 200000d4 {\n"
+ "> +               clk_gates1: gate-clk@200000d4 {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000d4 0x4>;\n"
  "> +                       clocks = <&xin24m>, <&xin24m>,\n"
@@ -139,7 +145,7 @@
  "> +                       #clock-cells = <1>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates2: gate-clk at 200000d8 {\n"
+ "> +               clk_gates2: gate-clk@200000d8 {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000d8 0x4>;\n"
  "> +                       clocks = <&clk_gates2 1>, <&dummy>,\n"
@@ -164,7 +170,7 @@
  "> +                       #clock-cells = <1>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates3: gate-clk at 200000dc {\n"
+ "> +               clk_gates3: gate-clk@200000dc {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000dc 0x4>;\n"
  "> +                       clocks = <&dummy>, <&dummy>,\n"
@@ -189,7 +195,7 @@
  "> +                       #clock-cells = <1>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates4: gate-clk at 200000e0 {\n"
+ "> +               clk_gates4: gate-clk@200000e0 {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000e0 0x4>;\n"
  "> +                       clocks = <&clk_gates2 2>, <&clk_gates2 3>,\n"
@@ -214,7 +220,7 @@
  "> +                       #clock-cells = <1>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates5: gate-clk at 200000e4 {\n"
+ "> +               clk_gates5: gate-clk@200000e4 {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000e4 0x4>;\n"
  "> +                       clocks = <&clk_gates0 3>, <&clk_gates2 1>,\n"
@@ -239,7 +245,7 @@
  "> +                       #clock-cells = <1>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates6: gate-clk at 200000e8 {\n"
+ "> +               clk_gates6: gate-clk@200000e8 {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000e8 0x4>;\n"
  "> +                       clocks = <&clk_gates3 0>, <&clk_gates0 4>,\n"
@@ -264,7 +270,7 @@
  "> +                       #clock-cells = <1>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates7: gate-clk at 200000ec {\n"
+ "> +               clk_gates7: gate-clk@200000ec {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000ec 0x4>;\n"
  "> +                       clocks = <&clk_gates2 2>, <&clk_gates0 4>,\n"
@@ -289,7 +295,7 @@
  "> +                       #clock-cells = <1>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates8: gate-clk at 200000f0 {\n"
+ "> +               clk_gates8: gate-clk@200000f0 {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000f0 0x4>;\n"
  "> +                       clocks = <&clk_gates0 5>, <&clk_gates0 5>,\n"
@@ -314,7 +320,7 @@
  "> +                       #clock-cells = <1>;\n"
  "> +               };\n"
  "> +\n"
- "> +               clk_gates9: gate-clk at 200000f4 {\n"
+ "> +               clk_gates9: gate-clk@200000f4 {\n"
  "> +                       compatible = \"rockchip,rk2928-gate-clk\";\n"
  "> +                       reg = <0x200000f4 0x4>;\n"
  "> +                       clocks = <&dummy>, <&clk_gates0 5>,\n"
@@ -343,7 +349,11 @@
  "> \n"
  "> _______________________________________________\n"
  "> linux-arm-kernel mailing list\n"
- "> linux-arm-kernel at lists.infradead.org\n"
- > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
+ "> linux-arm-kernel@lists.infradead.org\n"
+ "> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel\n"
+ "_______________________________________________\n"
+ "devicetree-discuss mailing list\n"
+ "devicetree-discuss@lists.ozlabs.org\n"
+ https://lists.ozlabs.org/listinfo/devicetree-discuss
 
-90761214c1679800a3413f0c8c03be5df0cdc01ba7e9b21fd2d79afdb8ee8c67
+bc9cb03dd77a37e5f7b4788ef9f6dc226bb92efb1b9a234a327f4300f6de4438
