From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerome Glisse Subject: Re: [PATCH 053/165] drm/radeon/cik: switch to type3 nop packet for compute rings Date: Wed, 26 Jun 2013 06:10:01 -0400 Message-ID: <20130626101000.GB2480@gmail.com> References: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> <1372253045-17042-54-git-send-email-alexdeucher@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qe0-f45.google.com (mail-qe0-f45.google.com [209.85.128.45]) by gabe.freedesktop.org (Postfix) with ESMTP id 9EAE2E6341 for ; Wed, 26 Jun 2013 08:14:55 -0700 (PDT) Received: by mail-qe0-f45.google.com with SMTP id w7so981289qeb.4 for ; Wed, 26 Jun 2013 08:14:55 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1372253045-17042-54-git-send-email-alexdeucher@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: alexdeucher@gmail.com Cc: Alex Deucher , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On Wed, Jun 26, 2013 at 09:22:13AM -0400, alexdeucher@gmail.com wrote: > From: Alex Deucher > > Type 2 packets are deprecated on CIK MEC and we should use > type 3 nop packets. Setting the count field to the max value > (0x3fff) indicates that only one dword should be skipped > like a type 2 packet. > > Signed-off-by: Alex Deucher What about adding same comment in the code and not only in git commit message. Reviewed-by: Jerome Glisse > --- > drivers/gpu/drm/radeon/cik.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index 9d2d6bb..08dc4c2 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -5470,7 +5470,7 @@ static int cik_startup(struct radeon_device *rdev) > ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; > r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, > CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR, > - 0, 0xfffff, RADEON_CP_PACKET2); > + 0, 0xfffff, PACKET3(PACKET3_NOP, 0x3FFF)); > if (r) > return r; > ring->me = 1; /* first MEC */ > @@ -5484,7 +5484,7 @@ static int cik_startup(struct radeon_device *rdev) > ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; > r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, > CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR, > - 0, 0xffffffff, RADEON_CP_PACKET2); > + 0, 0xffffffff, PACKET3(PACKET3_NOP, 0x3FFF)); > if (r) > return r; > /* dGPU only have 1 MEC */ > -- > 1.7.7.5 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel