From: Sughosh Ganu <urwithsughosh@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] TLB mapping for pcie mem space for fsl corenet processors
Date: Thu, 4 Jul 2013 23:43:29 +0530 [thread overview]
Message-ID: <20130704181329.GA8752@Hardy> (raw)
hi,
The tlb entries for the pcie mem space for the corenet SoC's is done
for 1.5GiB but certain boards use all the 4 pcie controller
instantiations, and each controller is assigned 512MiB size in the
config files. Should the tlb entries not map 2GiB space as against
1.5GiB. Am i missing something. Thanks.
-sughosh
next reply other threads:[~2013-07-04 18:13 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-04 18:13 Sughosh Ganu [this message]
2013-07-08 19:07 ` [U-Boot] TLB mapping for pcie mem space for fsl corenet processors Scott Wood
2013-07-08 19:32 ` Sughosh Ganu
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