diff for duplicates of <20130706013547.3ce7280b@skate> diff --git a/a/1.txt b/N1/1.txt index 33713ab..c8cac7f 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,7 +3,7 @@ Jason, Arnd, On Fri, 5 Jul 2013 18:39:11 -0300, Ezequiel Garcia wrote: > See the previous version of this patchset for further context: > -> http://www.mail-archive.com/devicetree-discuss at lists.ozlabs.org/msg35753.html +> http://www.mail-archive.com/devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org/msg35753.html > > This new proposal is an attempt to address some issues raised about the PCIe > 'fake' windows mapping present in the previous version. @@ -56,7 +56,7 @@ On Fri, 5 Jul 2013 18:39:11 -0300, Ezequiel Garcia wrote: > 0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>; > > -> pcie at 1,0 { +> pcie@1,0 { > /* Port 0, Lane 0 */ > status = "okay"; > }; @@ -68,11 +68,11 @@ On Fri, 5 Jul 2013 18:39:11 -0300, Ezequiel Garcia wrote: > #size-cells = <1>; > ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; > -> mbusc: mbus-controller at 20000 { +> mbusc: mbus-controller@20000 { > reg = <0x20000 0x100>, <0x20180 0x20>; > }; > -> interrupt-controller at 20000 { +> interrupt-controller@20000 { > reg = <0x20a00 0x2d0>, <0x21070 0x58>; > }; > }; @@ -128,7 +128,7 @@ up with: 0x81000000 2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; - pcie at 1,0 { + pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -145,7 +145,7 @@ up with: status = "disabled"; }; - pcie at 2,0 { + pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -169,11 +169,11 @@ up with: #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - mbusc: mbus-controller at 20000 { + mbusc: mbus-controller@20000 { reg = <0x20000 0x100>, <0x20180 0x20>; }; - interrupt-controller at 20000 { + interrupt-controller@20000 { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; }; @@ -200,7 +200,7 @@ I.e, the changes are : to encode the port number (in our example 1 for the first MEM and I/O ranges, and 2 for the next MEM and I/O ranges). - (3) A non-empty range property is added in the child pcie at x,y nodes to + (3) A non-empty range property is added in the child pcie@x,y nodes to translate back into regular PCIe addresses the child addresses described in the ranges property in pcie-controller. I.e, it simply translate (0x82000000 0 0) into (0x8200000 <port> 0). diff --git a/a/content_digest b/N1/content_digest index e936e2a..a492396 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,17 @@ "ref\01373060372-32357-1-git-send-email-ezequiel.garcia@free-electrons.com\0" - "From\0thomas.petazzoni@free-electrons.com (Thomas Petazzoni)\0" - "Subject\0[PATCH v6 00/21] MBus DT binding: PCIe strikes back\0" + "ref\01373060372-32357-1-git-send-email-ezequiel.garcia-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org\0" + "From\0Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Subject\0Re: [PATCH v6 00/21] MBus DT binding: PCIe strikes back\0" "Date\0Sat, 6 Jul 2013 01:35:47 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Jason Gunthorpe <jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>" + " Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>\0" + "Cc\0Lior Amsalem <alior-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>" + Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org> + Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org> + devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org + Maen Suleiman <maen-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + " Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" "\00:1\0" "b\0" "Jason, Arnd,\n" @@ -10,7 +19,7 @@ "On Fri, 5 Jul 2013 18:39:11 -0300, Ezequiel Garcia wrote:\n" "> See the previous version of this patchset for further context:\n" "> \n" - "> http://www.mail-archive.com/devicetree-discuss at lists.ozlabs.org/msg35753.html\n" + "> http://www.mail-archive.com/devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org/msg35753.html\n" "> \n" "> This new proposal is an attempt to address some issues raised about the PCIe\n" "> 'fake' windows mapping present in the previous version.\n" @@ -63,7 +72,7 @@ "> \t\t\t\t0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;\n" "> \n" "> \n" - "> \t\t\tpcie at 1,0 {\n" + "> \t\t\tpcie@1,0 {\n" "> \t\t\t\t/* Port 0, Lane 0 */\n" "> \t\t\t\tstatus = \"okay\";\n" "> \t\t\t};\n" @@ -75,11 +84,11 @@ "> \t\t\t#size-cells = <1>;\n" "> \t\t\tranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;\n" "> \n" - "> \t\t\tmbusc: mbus-controller at 20000 {\n" + "> \t\t\tmbusc: mbus-controller@20000 {\n" "> \t\t\t\treg = <0x20000 0x100>, <0x20180 0x20>;\n" "> \t\t\t};\n" "> \n" - "> \t\t\tinterrupt-controller at 20000 {\n" + "> \t\t\tinterrupt-controller@20000 {\n" "> \t\t\t reg = <0x20a00 0x2d0>, <0x21070 0x58>;\n" "> \t\t\t};\n" "> \t\t};\n" @@ -135,7 +144,7 @@ " 0x81000000 2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;\n" "\n" "\n" - " pcie at 1,0 {\n" + " pcie@1,0 {\n" " device_type = \"pci\";\n" " assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;\n" " reg = <0x0800 0 0 0 0>;\n" @@ -152,7 +161,7 @@ " status = \"disabled\";\n" " };\n" "\n" - " pcie at 2,0 {\n" + " pcie@2,0 {\n" " device_type = \"pci\";\n" " assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;\n" " reg = <0x1000 0 0 0 0>;\n" @@ -176,11 +185,11 @@ "\t\t\t#size-cells = <1>;\n" "\t\t\tranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;\n" "\n" - "\t\t\tmbusc: mbus-controller at 20000 {\n" + "\t\t\tmbusc: mbus-controller@20000 {\n" "\t\t\t\treg = <0x20000 0x100>, <0x20180 0x20>;\n" "\t\t\t};\n" "\n" - "\t\t\tinterrupt-controller at 20000 {\n" + "\t\t\tinterrupt-controller@20000 {\n" "\t\t\t reg = <0x20a00 0x2d0>, <0x21070 0x58>;\n" "\t\t\t};\n" "\t\t};\n" @@ -207,7 +216,7 @@ " to encode the port number (in our example 1 for the first MEM and I/O\n" " ranges, and 2 for the next MEM and I/O ranges).\n" "\n" - " (3) A non-empty range property is added in the child pcie at x,y nodes to\n" + " (3) A non-empty range property is added in the child pcie@x,y nodes to\n" " translate back into regular PCIe addresses the child addresses\n" " described in the ranges property in pcie-controller. I.e, it\n" " simply translate (0x82000000 0 0) into (0x8200000 <port> 0).\n" @@ -225,4 +234,4 @@ "development, consulting, training and support.\n" http://free-electrons.com -3a32841ba00c8f354060ebf42e72c51611ff35c50d20084c526d8f15dd30ea76 +56960aac618f3f0c873f4e9d4826179164412586199990245adffa8dc9dd1ae7
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