From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <benjamin.widawsky@intel.com>
Subject: [benjamin.widawsky@intel.com: intel_gpu_top broken for
 HSW. Ideas needed]
Date: Fri, 12 Jul 2013 10:12:39 -0700
Message-ID: <20130712171239.GA15328@intel.com>
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FWD'd from our internal list now that we have more insight.
----- Forwarded message from Ben Widawsky <benjamin.widawsky@intel.com> -----

Date: Thu, 11 Jul 2013 10:32:03 -0700
From: Ben Widawsky <benjamin.widawsky@intel.com>
To: linux-gfx@linux.intel.com
Subject: intel_gpu_top broken for HSW. Ideas needed
Message-ID: <20130711173202.GB8802@intel.com>

Hi everybody.

While investigating a hard hang on Haswell. Eero noticed that
intel_gpu_top helped to invoke the hang faster. I used this in my test
case to validation, and they are suspecting it is a known issue which we
have not yet worked around (and cannot reasonably workaround).

[internal bug sighting redacted]

To sum up, we cannot concurrently access registers within the same
cacheline. It has the potential to hit a known bug.

I see some choices:
1. Don't do anything.
2. Try to eliminate shared registers as much as possible. Instdone is
   used by the hangcheck, and we can eliminate hangcheck with a
   module parameter. Eero, can you try this as a workaround, btw?
3. Somehow make the kernel collect the top data and serialize access
   there.

Anyone else have input? I personally do not use top very much, so I
won't be volunteering to do any of these.

----- End forwarded message -----

-- 
Ben Widawsky, Intel Open Source Technology Center