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From: Markus Trippelsdorf <markus@trippelsdorf.de>
To: dri-devel@lists.freedesktop.org,
	Alex Deucher <alexander.deucher@amd.com>,
	Eric Biederman <ebiederm@xmission.com>
Subject: Commit f5d9b7f0f9 (fix r600_enable_sclk_control()) causes kexec issues
Date: Mon, 29 Jul 2013 09:51:32 +0200	[thread overview]
Message-ID: <20130729075132.GA354@x4> (raw)

On my test machine Xorg doesn't start anymore when I kexec into a
3.11.0-rc3 kernel.
On cold boot everything is fine:

[drm] Initialized drm 1.1.0 20060810
[drm] radeon kernel modesetting enabled.
[drm] initializing kernel modesetting (RS780 0x1002:0x9614 0x1043:0x834D).
[drm] register mmio base: 0xFBEE0000
[drm] register mmio size: 65536
ATOM BIOS: 113
radeon 0000:01:05.0: VRAM: 128M 0x00000000C0000000 - 0x00000000C7FFFFFF (128M used)
radeon 0000:01:05.0: GTT: 512M 0x00000000A0000000 - 0x00000000BFFFFFFF
[drm] Detected VRAM RAM=128M, BAR=128M
[drm] RAM width 32bits DDR
[TTM] Zone  kernel: Available graphics memory: 4082356 kiB
[TTM] Zone   dma32: Available graphics memory: 2097152 kiB
[TTM] Initializing pool allocator
[TTM] Initializing DMA pool allocator
[drm] radeon: 128M of VRAM memory ready
[drm] radeon: 512M of GTT memory ready.
[drm] GART: num cpu pages 131072, num gpu pages 131072
[drm] Loading RS780 Microcode
[drm] PCIE GART of 512M enabled (table at 0x00000000C0040000).
radeon 0000:01:05.0: WB enabled
radeon 0000:01:05.0: fence driver on ring 0 use gpu addr 0x00000000a0000c00 and cpu addr 0xffff880215c45c00
radeon 0000:01:05.0: fence driver on ring 3 use gpu addr 0x00000000a0000c0c and cpu addr 0xffff880215c45c0c
[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[drm] Driver supports precise vblank timestamp query.
[drm] radeon: irq initialized.
radeon 0000:01:05.0: setting latency timer to 64
[drm] ring test on 0 succeeded in 0 usecs
[drm] ring test on 3 succeeded in 1 usecs
[drm] ib test on ring 0 succeeded in 0 usecs
[drm] ib test on ring 3 succeeded in 0 usecs
[drm] Radeon Display Connectors
[drm] Connector 0:
[drm]   VGA-1
[drm]   DDC: 0x7e40 0x7e40 0x7e44 0x7e44 0x7e48 0x7e48 0x7e4c 0x7e4c
[drm]   Encoders:
[drm]     CRT1: INTERNAL_KLDSCP_DAC1
[drm] Connector 1:
[drm]   DVI-D-1
[drm]   HPD3
[drm]   DDC: 0x7e50 0x7e50 0x7e54 0x7e54 0x7e58 0x7e58 0x7e5c 0x7e5c
[drm]   Encoders:
[drm]     DFP3: INTERNAL_KLDSCP_LVTMA
== power state 0 ==
        ui class: none
        internal class: boot 
        caps: video 
        uvd    vclk: 0 dclk: 0
                power level 0    sclk: 50000 vddc_index: 2
                power level 1    sclk: 50000 vddc_index: 2
        status: c r b 
== power state 1 ==
        ui class: performance
        internal class: none
        caps: video 
        uvd    vclk: 0 dclk: 0
                power level 0    sclk: 50000 vddc_index: 1
                power level 1    sclk: 70000 vddc_index: 2
        status: 
== power state 2 ==
        ui class: none
        internal class: uvd 
        caps: video 
        uvd    vclk: 53300 dclk: 40000
                power level 0    sclk: 50000 vddc_index: 1
                power level 1    sclk: 50000 vddc_index: 1
        status: 
switching from power state:
        ui class: none
        internal class: boot 
        caps: video 
        uvd    vclk: 0 dclk: 0
                power level 0    sclk: 50000 vddc_index: 2
                power level 1    sclk: 50000 vddc_index: 2
        status: c b 
switching to power state:
        ui class: performance
        internal class: none
        caps: video 
        uvd    vclk: 0 dclk: 0
                power level 0    sclk: 50000 vddc_index: 1
                power level 1    sclk: 70000 vddc_index: 2
        status: r 
[drm] radeon: dpm initialized
[drm] fb mappable at 0xF0142000
[drm] vram apper at 0xF0000000
[drm] size 7299072
[drm] fb depth is 24
[drm]    pitch is 6912

But after I run kexec things go wrong:

[drm] Initialized drm 1.1.0 20060810
[drm] radeon kernel modesetting enabled.
[drm] initializing kernel modesetting (RS780 0x1002:0x9614 0x1043:0x834D).
[drm] register mmio base: 0xFBEE0000
[drm] register mmio size: 65536
ATOM BIOS: 113
radeon 0000:01:05.0: VRAM: 128M 0x00000000C0000000 - 0x00000000C7FFFFFF (128M used)
radeon 0000:01:05.0: GTT: 512M 0x00000000A0000000 - 0x00000000BFFFFFFF
[drm] Detected VRAM RAM=128M, BAR=128M
[drm] RAM width 32bits DDR
[TTM] Zone  kernel: Available graphics memory: 4082356 kiB
[TTM] Zone   dma32: Available graphics memory: 2097152 kiB
[TTM] Initializing pool allocator
[TTM] Initializing DMA pool allocator
[drm] radeon: 128M of VRAM memory ready
[drm] radeon: 512M of GTT memory ready.
[drm] GART: num cpu pages 131072, num gpu pages 131072
[drm] Loading RS780 Microcode
[drm] PCIE GART of 512M enabled (table at 0x00000000C0040000).
radeon 0000:01:05.0: WB enabled
radeon 0000:01:05.0: fence driver on ring 0 use gpu addr 0x00000000a0000c00 and cpu addr 0xffff880215c45c00
radeon 0000:01:05.0: fence driver on ring 3 use gpu addr 0x00000000a0000c0c and cpu addr 0xffff880215c45c0c
[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[drm] Driver supports precise vblank timestamp query.
[drm] radeon: irq initialized.
radeon 0000:01:05.0: setting latency timer to 64
[drm] ring test on 0 succeeded in 0 usecs
[drm:r600_dma_ring_test] *ERROR* radeon: ring 3 test failed (0xCAFEDEAD)
radeon 0000:01:05.0: disabling GPU acceleration
radeon 0000:01:05.0: ffff8802161eb400 unpin not necessary
[drm] Radeon Display Connectors
[drm] Connector 0:
[drm]   VGA-1
[drm]   DDC: 0x7e40 0x7e40 0x7e44 0x7e44 0x7e48 0x7e48 0x7e4c 0x7e4c
[drm]   Encoders:
[drm]     CRT1: INTERNAL_KLDSCP_DAC1
[drm] Connector 1:
[drm]   DVI-D-1
[drm]   HPD3
[drm]   DDC: 0x7e50 0x7e50 0x7e54 0x7e54 0x7e58 0x7e58 0x7e5c 0x7e5c
[drm]   Encoders:
[drm]     DFP3: INTERNAL_KLDSCP_LVTMA
== power state 0 ==
        ui class: none
        internal class: boot 
        caps: video 
        uvd    vclk: 0 dclk: 0
                power level 0    sclk: 50000 vddc_index: 2
                power level 1    sclk: 50000 vddc_index: 2
        status: c r b 
== power state 1 ==
        ui class: performance
        internal class: none
        caps: video 
        uvd    vclk: 0 dclk: 0
                power level 0    sclk: 50000 vddc_index: 1
                power level 1    sclk: 70000 vddc_index: 2
        status: 
== power state 2 ==
        ui class: none
        internal class: uvd 
        caps: video 
        uvd    vclk: 53300 dclk: 40000
                power level 0    sclk: 50000 vddc_index: 1
                power level 1    sclk: 50000 vddc_index: 1
        status: 
[drm:radeon_pm_init_dpm] *ERROR* radeon: dpm initialization failed
[drm] fb mappable at 0xF0142000
[drm] vram apper at 0xF0000000
[drm] size 7299072
[drm] fb depth is 24
[drm]    pitch is 6912

>From Xorg.0.log:
...
[     5.217] (II) RADEON(0): VRAM usage limit set to 104864K
[     5.218] (==) RADEON(0): Backing store disabled
[     5.218] (WW) RADEON(0): Direct rendering disabled
[     5.218] (II) RADEON(0): Acceleration disabled
[     5.218] (==) RADEON(0): DPMS enabled
[     5.218] (==) RADEON(0): Silken mouse enabled
[     5.218] (II) RADEON(0): RandR 1.2 enabled, ignore the following RandR disabled message.
[     5.219] (--) RandR disabled
[     5.235] (II) AIGLX: Screen 0 is not DRI2 capable
[     5.235] (II) AIGLX: Screen 0 is not DRI capable
[     5.248] (II) AIGLX: Loaded and initialized swrast
[     5.248] (II) GLX: Initialized DRISWRAST GL provider for screen 0
[     5.252] (EE) RADEON(0): Rotation requires acceleration!
[     5.252] (EE) 
Fatal server error:
[     5.252] (EE) failed to create screen resources(EE) 
[     5.252] (EE) 
Please consult the The X.Org Foundation support 
         at http://wiki.x.org
 for help. 
[     5.252] (EE) Please also check the log file at "/var/log/Xorg.0.log" for additional information.
[     5.252] (EE) 
[     5.436] (EE) Server terminated with error (1). Closing log file.

I've bisected the issue to:
 commit f5d9b7f0f93c6a7d40750b8b5528a1e0f0c678fb
 Author: Alex Deucher <alexander.deucher@amd.com>
 Date:   Thu Jul 25 21:46:21 2013 -0400

    drm/radeon/dpm: fix r600_enable_sclk_control()
    
    Actually program the correct register to enable
    engine clock scaling control.
    
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Reverting this commit on top of rc3 "fixes" the problem for me.

-- 
Markus

             reply	other threads:[~2013-07-29  7:51 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-29  7:51 Markus Trippelsdorf [this message]
2013-07-29 13:58 ` Commit f5d9b7f0f9 (fix r600_enable_sclk_control()) causes kexec issues Alex Deucher
2013-07-29 14:09   ` Markus Trippelsdorf
2013-07-29 14:18     ` Alex Deucher
2013-07-29 15:50       ` Eric W. Biederman
2013-07-29 18:02         ` Alex Deucher
2013-07-29 18:10           ` Eric W. Biederman
2013-07-29 19:53             ` Alex Deucher
2013-07-29 19:58               ` Markus Trippelsdorf
2013-07-30 11:27               ` Markus Trippelsdorf
2013-07-30 11:57                 ` Markus Trippelsdorf
2013-07-30 14:53                 ` Alex Deucher
2013-07-30 18:46                   ` Markus Trippelsdorf
2013-07-30 20:56                     ` Markus Trippelsdorf
2013-07-31  9:19                       ` Joshua C.
2013-07-29 16:14       ` Joshua C.
2013-07-29 16:35         ` Markus Trippelsdorf
2013-07-29 17:58         ` Alex Deucher

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