From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 03/15] drm/i915: port i965_irq_uninstall go
 INTEL_IRQ_REG_RESET
Date: Mon, 29 Jul 2013 14:47:55 +0300
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To: Paulo Zanoni <przanoni@gmail.com>
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On Wed, Jul 24, 2013 at 11:14:57AM -0300, Paulo Zanoni wrote:
> 2013/7/24 Chris Wilson <chris@chris-wilson.co.uk>:
> > On Tue, Jul 23, 2013 at 07:33:43PM -0300, Paulo Zanoni wrote:
> >> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >>
> >> The problem here is that we have the PIPESTAT registers between IER
> >> and IIR, so when we use intel_irq_reg_reset we flip the order used to
> >> reset IIR and PIPESTAT. That should be safe since after we clear
> >> IMR/IER we won't get any other IIR/PIPESTAT interrupts. Still, the
> >> change is on its own patch, so it should be easy to bisect and revert
> >> if needed.
> >
> > This is wrong. PIPESTAT needs to be cleared before IIR.
> =

> Yeah, you're right. I see that if we want to make all the code
> touching pipestat consistent we could probably dedicate a full patch
> series to it. The fact that PIPESTAT needs to be disabled after
> IER/IMR but before IIR also kinda breaks my macros, I'll have to
> rethink them now.

Why would it need to be cleared before IMR/IER? Clearing PIPESTAT first,
them IER/IMR, and finally IIR should be OK.

-- =

Ville Syrj=E4l=E4
Intel OTC