From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2 14/17] drm/i915: Print the watermark latencies during init Date: Fri, 2 Aug 2013 17:55:06 +0300 Message-ID: <20130802145506.GM5004@intel.com> References: <1375363135-20618-1-git-send-email-ville.syrjala@linux.intel.com> <1375363135-20618-15-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 58F58E604E for ; Fri, 2 Aug 2013 07:55:10 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Aug 02, 2013 at 11:41:31AM -0300, Paulo Zanoni wrote: > 2013/8/1 : > > From: Ville Syrj=E4l=E4 > > > > Seeing the watermark latency values in dmesg might help sometimes. > > > > v2: Use DRM_ERROR() when expected latency values are missing > > > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_pm.c | 37 +++++++++++++++++++++++++++++++++= ++++ > > 1 file changed, 37 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index f754ca2..53967ef 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -2394,6 +2394,39 @@ static void intel_fixup_cur_wm_latency(struct dr= m_device *dev, uint16_t wm[5]) > > wm[3] *=3D 2; > > } > > > > +static void intel_print_wm_latency(struct drm_device *dev, > > + const char *name, > > + const uint16_t wm[5]) > > +{ > > + int level, max_level; > > + > > + /* how many WM levels are we expecting */ > > + if (IS_HASWELL(dev)) > > + max_level =3D 4; > > + else if (INTEL_INFO(dev)->gen >=3D 6) > > + max_level =3D 3; > > + else > > + max_level =3D 2; > > + > > + for (level =3D 0; level <=3D max_level; level++) { > > + unsigned int latency =3D wm[level]; > > + > > + if (latency =3D=3D 0) { > > + DRM_ERROR("%s WM%d latency not provided\n", > > + name, level); > = > On your last email you mentioned that we may start getting bug reports > that we can't do anything about. You're right, I guess if we start > getting these reports we should probably tune the message to > DRM_DEBUG_KMS then. Yeah. Another idea that I had is that we could store the max WM level into dev_priv based on which levels have non-zero latencies. That way we'd avoid ever hitting the case where we try to compute a watermark w/ latency=3D=3D0. But I didn't implement this yet. > = > Reviewed-by: Paulo Zanoni > = > > + continue; > > + } > > + > > + /* WM1+ latency values in 0.5us units */ > > + if (level > 0) > > + latency *=3D 5; > > + > > + DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", > > + name, level, wm[level], > > + latency / 10, latency % 10); > > + } > > +} > > + > > static void intel_setup_wm_latency(struct drm_device *dev) > > { > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > @@ -2407,6 +2440,10 @@ static void intel_setup_wm_latency(struct drm_de= vice *dev) > > > > intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); > > intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); > > + > > + intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency= ); > > + intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); > > + intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); > > } > > > > static void hsw_compute_wm_parameters(struct drm_device *dev, > > -- > > 1.8.1.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > = > = > -- = > Paulo Zanoni -- = Ville Syrj=E4l=E4 Intel OTC