diff for duplicates of <20130802223000.6450.97817@quantum> diff --git a/a/1.txt b/N1/1.txt index ec0f8dd..e6ae478 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,12 +1,10 @@ Quoting Gerhard Sittig (2013-07-22 05:14:40) > the common clock drivers were motivated/initiated by ARM development > and apparently assume little endian peripherals -> = - +> > wrap register/peripherals access in the common code (div, gate, mux) > in preparation of adding COMMON_CLK support for other platforms -> = - +> > Signed-off-by: Gerhard Sittig <gsi@denx.de> I've taken this into clk-next for testing. regmap deserves investigation @@ -23,76 +21,63 @@ Mike > drivers/clk/clk-mux.c | 6 +++--- > include/linux/clk-provider.h | 17 +++++++++++++++++ > 4 files changed, 26 insertions(+), 9 deletions(-) -> = - +> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c > index 6d55eb2..2c07061 100644 > --- a/drivers/clk/clk-divider.c > +++ b/drivers/clk/clk-divider.c -> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct c= -lk_hw *hw, -> struct clk_divider *divider =3D to_clk_divider(hw); +> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, +> struct clk_divider *divider = to_clk_divider(hw); > unsigned int div, val; -> = - -> - val =3D readl(divider->reg) >> divider->shift; -> + val =3D clk_readl(divider->reg) >> divider->shift; -> val &=3D div_mask(divider); -> = - -> div =3D _get_div(divider, val); -> @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, = -unsigned long rate, +> +> - val = readl(divider->reg) >> divider->shift; +> + val = clk_readl(divider->reg) >> divider->shift; +> val &= div_mask(divider); +> +> div = _get_div(divider, val); +> @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, > if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { -> val =3D div_mask(divider) << (divider->shift + 16); +> val = div_mask(divider) << (divider->shift + 16); > } else { -> - val =3D readl(divider->reg); -> + val =3D clk_readl(divider->reg); -> val &=3D ~(div_mask(divider) << divider->shift); +> - val = readl(divider->reg); +> + val = clk_readl(divider->reg); +> val &= ~(div_mask(divider) << divider->shift); > } -> val |=3D value << divider->shift; +> val |= value << divider->shift; > - writel(val, divider->reg); > + clk_writel(val, divider->reg); -> = - +> > if (divider->lock) > spin_unlock_irqrestore(divider->lock, flags); > diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c > index 790306e..b7fbd96 100644 > --- a/drivers/clk/clk-gate.c > +++ b/drivers/clk/clk-gate.c -> @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e= -nable) +> @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) > if (set) -> reg |=3D BIT(gate->bit_idx); +> reg |= BIT(gate->bit_idx); > } else { -> - reg =3D readl(gate->reg); -> + reg =3D clk_readl(gate->reg); -> = - +> - reg = readl(gate->reg); +> + reg = clk_readl(gate->reg); +> > if (set) -> reg |=3D BIT(gate->bit_idx); -> @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e= -nable) -> reg &=3D ~BIT(gate->bit_idx); +> reg |= BIT(gate->bit_idx); +> @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) +> reg &= ~BIT(gate->bit_idx); > } -> = - +> > - writel(reg, gate->reg); > + clk_writel(reg, gate->reg); -> = - +> > if (gate->lock) > spin_unlock_irqrestore(gate->lock, flags); > @@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw) > u32 reg; -> struct clk_gate *gate =3D to_clk_gate(hw); -> = - -> - reg =3D readl(gate->reg); -> + reg =3D clk_readl(gate->reg); -> = - +> struct clk_gate *gate = to_clk_gate(hw); +> +> - reg = readl(gate->reg); +> + reg = clk_readl(gate->reg); +> > /* if a set bit disables this clk, flip it before masking */ > if (gate->flags & CLK_GATE_SET_TO_DISABLE) > diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c @@ -100,30 +85,26 @@ nable) > --- a/drivers/clk/clk-mux.c > +++ b/drivers/clk/clk-mux.c > @@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) -> * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock,= - so -> * val =3D 0x4 really means "bit 2, index starts at bit 0" +> * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so +> * val = 0x4 really means "bit 2, index starts at bit 0" > */ -> - val =3D readl(mux->reg) >> mux->shift; -> + val =3D clk_readl(mux->reg) >> mux->shift; -> val &=3D mux->mask; -> = - +> - val = readl(mux->reg) >> mux->shift; +> + val = clk_readl(mux->reg) >> mux->shift; +> val &= mux->mask; +> > if (mux->table) { -> @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 i= -ndex) +> @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) > if (mux->flags & CLK_MUX_HIWORD_MASK) { -> val =3D mux->mask << (mux->shift + 16); +> val = mux->mask << (mux->shift + 16); > } else { -> - val =3D readl(mux->reg); -> + val =3D clk_readl(mux->reg); -> val &=3D ~(mux->mask << mux->shift); +> - val = readl(mux->reg); +> + val = clk_readl(mux->reg); +> val &= ~(mux->mask << mux->shift); > } -> val |=3D index << mux->shift; +> val |= index << mux->shift; > - writel(val, mux->reg); > + clk_writel(val, mux->reg); -> = - +> > if (mux->lock) > spin_unlock_irqrestore(mux->lock, flags); > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h @@ -132,17 +113,13 @@ ndex) > +++ b/include/linux/clk-provider.h > @@ -12,6 +12,7 @@ > #define __LINUX_CLK_PROVIDER_H -> = - +> > #include <linux/clk.h> > +#include <linux/io.h> -> = - +> > #ifdef CONFIG_COMMON_CLK -> = - -> @@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(str= -uct device_node *np, +> +> @@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np, > #define of_clk_init(matches) \ > { while (0); } > #endif /* CONFIG_OF */ @@ -164,6 +141,5 @@ uct device_node *np, > + > #endif /* CONFIG_COMMON_CLK */ > #endif /* CLK_PROVIDER_H */ -> -- = - +> -- > 1.7.10.4 diff --git a/a/content_digest b/N1/content_digest index 426dc10..0e58f89 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,35 +1,19 @@ "ref\01374166855-7280-1-git-send-email-gsi@denx.de\0" "ref\01374495298-22019-1-git-send-email-gsi@denx.de\0" "ref\01374495298-22019-14-git-send-email-gsi@denx.de\0" - "From\0Mike Turquette <mturquette@linaro.org>\0" - "Subject\0Re: [PATCH v3 13/31] clk: wrap I/O access for improved portability\0" + "From\0mturquette@linaro.org (Mike Turquette)\0" + "Subject\0[PATCH v3 13/31] clk: wrap I/O access for improved portability\0" "Date\0Fri, 02 Aug 2013 15:30:00 -0700\0" - "To\0Gerhard Sittig <gsi@denx.de>" - linuxppc-dev@lists.ozlabs.org - Anatolij Gustschin <agust@denx.de> - linux-arm-kernel@lists.infradead.org - " devicetree-discuss@lists.ozlabs.org\0" - "Cc\0Detlev Zundel <dzu@denx.de>" - Wolfram Sang <wsa@the-dreams.de> - Greg Kroah-Hartman <gregkh@linuxfoundation.org> - Gerhard Sittig <gsi@denx.de> - Rob Herring <rob.herring@calxeda.com> - Mark Brown <broonie@kernel.org> - Marc Kleine-Budde <mkl@pengutronix.de> - David Woodhouse <dwmw2@infradead.org> - Wolfgang Grandegger <wg@grandegger.com> - " Mauro Carvalho Chehab <m.chehab@samsung.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Gerhard Sittig (2013-07-22 05:14:40)\n" "> the common clock drivers were motivated/initiated by ARM development\n" "> and apparently assume little endian peripherals\n" - "> =\n" - "\n" + "> \n" "> wrap register/peripherals access in the common code (div, gate, mux)\n" "> in preparation of adding COMMON_CLK support for other platforms\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Gerhard Sittig <gsi@denx.de>\n" "\n" "I've taken this into clk-next for testing. regmap deserves investigation\n" @@ -46,76 +30,63 @@ "> drivers/clk/clk-mux.c | 6 +++---\n" "> include/linux/clk-provider.h | 17 +++++++++++++++++\n" "> 4 files changed, 26 insertions(+), 9 deletions(-)\n" - "> =\n" - "\n" + "> \n" "> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c\n" "> index 6d55eb2..2c07061 100644\n" "> --- a/drivers/clk/clk-divider.c\n" "> +++ b/drivers/clk/clk-divider.c\n" - "> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct c=\n" - "lk_hw *hw,\n" - "> struct clk_divider *divider =3D to_clk_divider(hw);\n" + "> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,\n" + "> struct clk_divider *divider = to_clk_divider(hw);\n" "> unsigned int div, val;\n" - "> =\n" - "\n" - "> - val =3D readl(divider->reg) >> divider->shift;\n" - "> + val =3D clk_readl(divider->reg) >> divider->shift;\n" - "> val &=3D div_mask(divider);\n" - "> =\n" - "\n" - "> div =3D _get_div(divider, val);\n" - "> @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, =\n" - "unsigned long rate,\n" + "> \n" + "> - val = readl(divider->reg) >> divider->shift;\n" + "> + val = clk_readl(divider->reg) >> divider->shift;\n" + "> val &= div_mask(divider);\n" + "> \n" + "> div = _get_div(divider, val);\n" + "> @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,\n" "> if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {\n" - "> val =3D div_mask(divider) << (divider->shift + 16);\n" + "> val = div_mask(divider) << (divider->shift + 16);\n" "> } else {\n" - "> - val =3D readl(divider->reg);\n" - "> + val =3D clk_readl(divider->reg);\n" - "> val &=3D ~(div_mask(divider) << divider->shift);\n" + "> - val = readl(divider->reg);\n" + "> + val = clk_readl(divider->reg);\n" + "> val &= ~(div_mask(divider) << divider->shift);\n" "> }\n" - "> val |=3D value << divider->shift;\n" + "> val |= value << divider->shift;\n" "> - writel(val, divider->reg);\n" "> + clk_writel(val, divider->reg);\n" - "> =\n" - "\n" + "> \n" "> if (divider->lock)\n" "> spin_unlock_irqrestore(divider->lock, flags);\n" "> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c\n" "> index 790306e..b7fbd96 100644\n" "> --- a/drivers/clk/clk-gate.c\n" "> +++ b/drivers/clk/clk-gate.c\n" - "> @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e=\n" - "nable)\n" + "> @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)\n" "> if (set)\n" - "> reg |=3D BIT(gate->bit_idx);\n" + "> reg |= BIT(gate->bit_idx);\n" "> } else {\n" - "> - reg =3D readl(gate->reg);\n" - "> + reg =3D clk_readl(gate->reg);\n" - "> =\n" - "\n" + "> - reg = readl(gate->reg);\n" + "> + reg = clk_readl(gate->reg);\n" + "> \n" "> if (set)\n" - "> reg |=3D BIT(gate->bit_idx);\n" - "> @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e=\n" - "nable)\n" - "> reg &=3D ~BIT(gate->bit_idx);\n" + "> reg |= BIT(gate->bit_idx);\n" + "> @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)\n" + "> reg &= ~BIT(gate->bit_idx);\n" "> }\n" - "> =\n" - "\n" + "> \n" "> - writel(reg, gate->reg);\n" "> + clk_writel(reg, gate->reg);\n" - "> =\n" - "\n" + "> \n" "> if (gate->lock)\n" "> spin_unlock_irqrestore(gate->lock, flags);\n" "> @@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)\n" "> u32 reg;\n" - "> struct clk_gate *gate =3D to_clk_gate(hw);\n" - "> =\n" - "\n" - "> - reg =3D readl(gate->reg);\n" - "> + reg =3D clk_readl(gate->reg);\n" - "> =\n" - "\n" + "> struct clk_gate *gate = to_clk_gate(hw);\n" + "> \n" + "> - reg = readl(gate->reg);\n" + "> + reg = clk_readl(gate->reg);\n" + "> \n" "> /* if a set bit disables this clk, flip it before masking */\n" "> if (gate->flags & CLK_GATE_SET_TO_DISABLE)\n" "> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c\n" @@ -123,30 +94,26 @@ "> --- a/drivers/clk/clk-mux.c\n" "> +++ b/drivers/clk/clk-mux.c\n" "> @@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)\n" - "> * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock,=\n" - " so\n" - "> * val =3D 0x4 really means \"bit 2, index starts at bit 0\"\n" + "> * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so\n" + "> * val = 0x4 really means \"bit 2, index starts at bit 0\"\n" "> */\n" - "> - val =3D readl(mux->reg) >> mux->shift;\n" - "> + val =3D clk_readl(mux->reg) >> mux->shift;\n" - "> val &=3D mux->mask;\n" - "> =\n" - "\n" + "> - val = readl(mux->reg) >> mux->shift;\n" + "> + val = clk_readl(mux->reg) >> mux->shift;\n" + "> val &= mux->mask;\n" + "> \n" "> if (mux->table) {\n" - "> @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 i=\n" - "ndex)\n" + "> @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)\n" "> if (mux->flags & CLK_MUX_HIWORD_MASK) {\n" - "> val =3D mux->mask << (mux->shift + 16);\n" + "> val = mux->mask << (mux->shift + 16);\n" "> } else {\n" - "> - val =3D readl(mux->reg);\n" - "> + val =3D clk_readl(mux->reg);\n" - "> val &=3D ~(mux->mask << mux->shift);\n" + "> - val = readl(mux->reg);\n" + "> + val = clk_readl(mux->reg);\n" + "> val &= ~(mux->mask << mux->shift);\n" "> }\n" - "> val |=3D index << mux->shift;\n" + "> val |= index << mux->shift;\n" "> - writel(val, mux->reg);\n" "> + clk_writel(val, mux->reg);\n" - "> =\n" - "\n" + "> \n" "> if (mux->lock)\n" "> spin_unlock_irqrestore(mux->lock, flags);\n" "> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h\n" @@ -155,17 +122,13 @@ "> +++ b/include/linux/clk-provider.h\n" "> @@ -12,6 +12,7 @@\n" "> #define __LINUX_CLK_PROVIDER_H\n" - "> =\n" - "\n" + "> \n" "> #include <linux/clk.h>\n" "> +#include <linux/io.h>\n" - "> =\n" - "\n" + "> \n" "> #ifdef CONFIG_COMMON_CLK\n" - "> =\n" - "\n" - "> @@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(str=\n" - "uct device_node *np,\n" + "> \n" + "> @@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,\n" "> #define of_clk_init(matches) \\\n" "> { while (0); }\n" "> #endif /* CONFIG_OF */\n" @@ -187,8 +150,7 @@ "> +\n" "> #endif /* CONFIG_COMMON_CLK */\n" "> #endif /* CLK_PROVIDER_H */\n" - "> -- =\n" - "\n" + "> -- \n" > 1.7.10.4 -2e449599609f8e4de587e69c4d3433589f43d0d13dcdb6c4be4a038df2c848c2 +f1ebb33a304cf3646aa726b2c975f76a09c1924f0b70a3cb2605b9b28f8fb320
diff --git a/a/1.txt b/N2/1.txt index ec0f8dd..e6ae478 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,12 +1,10 @@ Quoting Gerhard Sittig (2013-07-22 05:14:40) > the common clock drivers were motivated/initiated by ARM development > and apparently assume little endian peripherals -> = - +> > wrap register/peripherals access in the common code (div, gate, mux) > in preparation of adding COMMON_CLK support for other platforms -> = - +> > Signed-off-by: Gerhard Sittig <gsi@denx.de> I've taken this into clk-next for testing. regmap deserves investigation @@ -23,76 +21,63 @@ Mike > drivers/clk/clk-mux.c | 6 +++--- > include/linux/clk-provider.h | 17 +++++++++++++++++ > 4 files changed, 26 insertions(+), 9 deletions(-) -> = - +> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c > index 6d55eb2..2c07061 100644 > --- a/drivers/clk/clk-divider.c > +++ b/drivers/clk/clk-divider.c -> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct c= -lk_hw *hw, -> struct clk_divider *divider =3D to_clk_divider(hw); +> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, +> struct clk_divider *divider = to_clk_divider(hw); > unsigned int div, val; -> = - -> - val =3D readl(divider->reg) >> divider->shift; -> + val =3D clk_readl(divider->reg) >> divider->shift; -> val &=3D div_mask(divider); -> = - -> div =3D _get_div(divider, val); -> @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, = -unsigned long rate, +> +> - val = readl(divider->reg) >> divider->shift; +> + val = clk_readl(divider->reg) >> divider->shift; +> val &= div_mask(divider); +> +> div = _get_div(divider, val); +> @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, > if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { -> val =3D div_mask(divider) << (divider->shift + 16); +> val = div_mask(divider) << (divider->shift + 16); > } else { -> - val =3D readl(divider->reg); -> + val =3D clk_readl(divider->reg); -> val &=3D ~(div_mask(divider) << divider->shift); +> - val = readl(divider->reg); +> + val = clk_readl(divider->reg); +> val &= ~(div_mask(divider) << divider->shift); > } -> val |=3D value << divider->shift; +> val |= value << divider->shift; > - writel(val, divider->reg); > + clk_writel(val, divider->reg); -> = - +> > if (divider->lock) > spin_unlock_irqrestore(divider->lock, flags); > diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c > index 790306e..b7fbd96 100644 > --- a/drivers/clk/clk-gate.c > +++ b/drivers/clk/clk-gate.c -> @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e= -nable) +> @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) > if (set) -> reg |=3D BIT(gate->bit_idx); +> reg |= BIT(gate->bit_idx); > } else { -> - reg =3D readl(gate->reg); -> + reg =3D clk_readl(gate->reg); -> = - +> - reg = readl(gate->reg); +> + reg = clk_readl(gate->reg); +> > if (set) -> reg |=3D BIT(gate->bit_idx); -> @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e= -nable) -> reg &=3D ~BIT(gate->bit_idx); +> reg |= BIT(gate->bit_idx); +> @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) +> reg &= ~BIT(gate->bit_idx); > } -> = - +> > - writel(reg, gate->reg); > + clk_writel(reg, gate->reg); -> = - +> > if (gate->lock) > spin_unlock_irqrestore(gate->lock, flags); > @@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw) > u32 reg; -> struct clk_gate *gate =3D to_clk_gate(hw); -> = - -> - reg =3D readl(gate->reg); -> + reg =3D clk_readl(gate->reg); -> = - +> struct clk_gate *gate = to_clk_gate(hw); +> +> - reg = readl(gate->reg); +> + reg = clk_readl(gate->reg); +> > /* if a set bit disables this clk, flip it before masking */ > if (gate->flags & CLK_GATE_SET_TO_DISABLE) > diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c @@ -100,30 +85,26 @@ nable) > --- a/drivers/clk/clk-mux.c > +++ b/drivers/clk/clk-mux.c > @@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) -> * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock,= - so -> * val =3D 0x4 really means "bit 2, index starts at bit 0" +> * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so +> * val = 0x4 really means "bit 2, index starts at bit 0" > */ -> - val =3D readl(mux->reg) >> mux->shift; -> + val =3D clk_readl(mux->reg) >> mux->shift; -> val &=3D mux->mask; -> = - +> - val = readl(mux->reg) >> mux->shift; +> + val = clk_readl(mux->reg) >> mux->shift; +> val &= mux->mask; +> > if (mux->table) { -> @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 i= -ndex) +> @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) > if (mux->flags & CLK_MUX_HIWORD_MASK) { -> val =3D mux->mask << (mux->shift + 16); +> val = mux->mask << (mux->shift + 16); > } else { -> - val =3D readl(mux->reg); -> + val =3D clk_readl(mux->reg); -> val &=3D ~(mux->mask << mux->shift); +> - val = readl(mux->reg); +> + val = clk_readl(mux->reg); +> val &= ~(mux->mask << mux->shift); > } -> val |=3D index << mux->shift; +> val |= index << mux->shift; > - writel(val, mux->reg); > + clk_writel(val, mux->reg); -> = - +> > if (mux->lock) > spin_unlock_irqrestore(mux->lock, flags); > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h @@ -132,17 +113,13 @@ ndex) > +++ b/include/linux/clk-provider.h > @@ -12,6 +12,7 @@ > #define __LINUX_CLK_PROVIDER_H -> = - +> > #include <linux/clk.h> > +#include <linux/io.h> -> = - +> > #ifdef CONFIG_COMMON_CLK -> = - -> @@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(str= -uct device_node *np, +> +> @@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np, > #define of_clk_init(matches) \ > { while (0); } > #endif /* CONFIG_OF */ @@ -164,6 +141,5 @@ uct device_node *np, > + > #endif /* CONFIG_COMMON_CLK */ > #endif /* CLK_PROVIDER_H */ -> -- = - +> -- > 1.7.10.4 diff --git a/a/content_digest b/N2/content_digest index 426dc10..963b84a 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -4,8 +4,7 @@ "From\0Mike Turquette <mturquette@linaro.org>\0" "Subject\0Re: [PATCH v3 13/31] clk: wrap I/O access for improved portability\0" "Date\0Fri, 02 Aug 2013 15:30:00 -0700\0" - "To\0Gerhard Sittig <gsi@denx.de>" - linuxppc-dev@lists.ozlabs.org + "To\0linuxppc-dev@lists.ozlabs.org" Anatolij Gustschin <agust@denx.de> linux-arm-kernel@lists.infradead.org " devicetree-discuss@lists.ozlabs.org\0" @@ -24,12 +23,10 @@ "Quoting Gerhard Sittig (2013-07-22 05:14:40)\n" "> the common clock drivers were motivated/initiated by ARM development\n" "> and apparently assume little endian peripherals\n" - "> =\n" - "\n" + "> \n" "> wrap register/peripherals access in the common code (div, gate, mux)\n" "> in preparation of adding COMMON_CLK support for other platforms\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Gerhard Sittig <gsi@denx.de>\n" "\n" "I've taken this into clk-next for testing. regmap deserves investigation\n" @@ -46,76 +43,63 @@ "> drivers/clk/clk-mux.c | 6 +++---\n" "> include/linux/clk-provider.h | 17 +++++++++++++++++\n" "> 4 files changed, 26 insertions(+), 9 deletions(-)\n" - "> =\n" - "\n" + "> \n" "> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c\n" "> index 6d55eb2..2c07061 100644\n" "> --- a/drivers/clk/clk-divider.c\n" "> +++ b/drivers/clk/clk-divider.c\n" - "> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct c=\n" - "lk_hw *hw,\n" - "> struct clk_divider *divider =3D to_clk_divider(hw);\n" + "> @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,\n" + "> struct clk_divider *divider = to_clk_divider(hw);\n" "> unsigned int div, val;\n" - "> =\n" - "\n" - "> - val =3D readl(divider->reg) >> divider->shift;\n" - "> + val =3D clk_readl(divider->reg) >> divider->shift;\n" - "> val &=3D div_mask(divider);\n" - "> =\n" - "\n" - "> div =3D _get_div(divider, val);\n" - "> @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, =\n" - "unsigned long rate,\n" + "> \n" + "> - val = readl(divider->reg) >> divider->shift;\n" + "> + val = clk_readl(divider->reg) >> divider->shift;\n" + "> val &= div_mask(divider);\n" + "> \n" + "> div = _get_div(divider, val);\n" + "> @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,\n" "> if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {\n" - "> val =3D div_mask(divider) << (divider->shift + 16);\n" + "> val = div_mask(divider) << (divider->shift + 16);\n" "> } else {\n" - "> - val =3D readl(divider->reg);\n" - "> + val =3D clk_readl(divider->reg);\n" - "> val &=3D ~(div_mask(divider) << divider->shift);\n" + "> - val = readl(divider->reg);\n" + "> + val = clk_readl(divider->reg);\n" + "> val &= ~(div_mask(divider) << divider->shift);\n" "> }\n" - "> val |=3D value << divider->shift;\n" + "> val |= value << divider->shift;\n" "> - writel(val, divider->reg);\n" "> + clk_writel(val, divider->reg);\n" - "> =\n" - "\n" + "> \n" "> if (divider->lock)\n" "> spin_unlock_irqrestore(divider->lock, flags);\n" "> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c\n" "> index 790306e..b7fbd96 100644\n" "> --- a/drivers/clk/clk-gate.c\n" "> +++ b/drivers/clk/clk-gate.c\n" - "> @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e=\n" - "nable)\n" + "> @@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)\n" "> if (set)\n" - "> reg |=3D BIT(gate->bit_idx);\n" + "> reg |= BIT(gate->bit_idx);\n" "> } else {\n" - "> - reg =3D readl(gate->reg);\n" - "> + reg =3D clk_readl(gate->reg);\n" - "> =\n" - "\n" + "> - reg = readl(gate->reg);\n" + "> + reg = clk_readl(gate->reg);\n" + "> \n" "> if (set)\n" - "> reg |=3D BIT(gate->bit_idx);\n" - "> @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int e=\n" - "nable)\n" - "> reg &=3D ~BIT(gate->bit_idx);\n" + "> reg |= BIT(gate->bit_idx);\n" + "> @@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)\n" + "> reg &= ~BIT(gate->bit_idx);\n" "> }\n" - "> =\n" - "\n" + "> \n" "> - writel(reg, gate->reg);\n" "> + clk_writel(reg, gate->reg);\n" - "> =\n" - "\n" + "> \n" "> if (gate->lock)\n" "> spin_unlock_irqrestore(gate->lock, flags);\n" "> @@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)\n" "> u32 reg;\n" - "> struct clk_gate *gate =3D to_clk_gate(hw);\n" - "> =\n" - "\n" - "> - reg =3D readl(gate->reg);\n" - "> + reg =3D clk_readl(gate->reg);\n" - "> =\n" - "\n" + "> struct clk_gate *gate = to_clk_gate(hw);\n" + "> \n" + "> - reg = readl(gate->reg);\n" + "> + reg = clk_readl(gate->reg);\n" + "> \n" "> /* if a set bit disables this clk, flip it before masking */\n" "> if (gate->flags & CLK_GATE_SET_TO_DISABLE)\n" "> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c\n" @@ -123,30 +107,26 @@ "> --- a/drivers/clk/clk-mux.c\n" "> +++ b/drivers/clk/clk-mux.c\n" "> @@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)\n" - "> * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock,=\n" - " so\n" - "> * val =3D 0x4 really means \"bit 2, index starts at bit 0\"\n" + "> * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so\n" + "> * val = 0x4 really means \"bit 2, index starts at bit 0\"\n" "> */\n" - "> - val =3D readl(mux->reg) >> mux->shift;\n" - "> + val =3D clk_readl(mux->reg) >> mux->shift;\n" - "> val &=3D mux->mask;\n" - "> =\n" - "\n" + "> - val = readl(mux->reg) >> mux->shift;\n" + "> + val = clk_readl(mux->reg) >> mux->shift;\n" + "> val &= mux->mask;\n" + "> \n" "> if (mux->table) {\n" - "> @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 i=\n" - "ndex)\n" + "> @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)\n" "> if (mux->flags & CLK_MUX_HIWORD_MASK) {\n" - "> val =3D mux->mask << (mux->shift + 16);\n" + "> val = mux->mask << (mux->shift + 16);\n" "> } else {\n" - "> - val =3D readl(mux->reg);\n" - "> + val =3D clk_readl(mux->reg);\n" - "> val &=3D ~(mux->mask << mux->shift);\n" + "> - val = readl(mux->reg);\n" + "> + val = clk_readl(mux->reg);\n" + "> val &= ~(mux->mask << mux->shift);\n" "> }\n" - "> val |=3D index << mux->shift;\n" + "> val |= index << mux->shift;\n" "> - writel(val, mux->reg);\n" "> + clk_writel(val, mux->reg);\n" - "> =\n" - "\n" + "> \n" "> if (mux->lock)\n" "> spin_unlock_irqrestore(mux->lock, flags);\n" "> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h\n" @@ -155,17 +135,13 @@ "> +++ b/include/linux/clk-provider.h\n" "> @@ -12,6 +12,7 @@\n" "> #define __LINUX_CLK_PROVIDER_H\n" - "> =\n" - "\n" + "> \n" "> #include <linux/clk.h>\n" "> +#include <linux/io.h>\n" - "> =\n" - "\n" + "> \n" "> #ifdef CONFIG_COMMON_CLK\n" - "> =\n" - "\n" - "> @@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(str=\n" - "uct device_node *np,\n" + "> \n" + "> @@ -490,5 +491,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,\n" "> #define of_clk_init(matches) \\\n" "> { while (0); }\n" "> #endif /* CONFIG_OF */\n" @@ -187,8 +163,7 @@ "> +\n" "> #endif /* CONFIG_COMMON_CLK */\n" "> #endif /* CLK_PROVIDER_H */\n" - "> -- =\n" - "\n" + "> -- \n" > 1.7.10.4 -2e449599609f8e4de587e69c4d3433589f43d0d13dcdb6c4be4a038df2c848c2 +2406e04579db513fd1889ae1ce1130b49eccf029b78b4a48eca9efbb770b31b5
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