diff for duplicates of <20130802234120.6450.57074@quantum> diff --git a/a/1.txt b/N1/1.txt index 794c672..8f0c0d5 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,361 +1,321 @@ Quoting Gerhard Sittig (2013-07-22 05:14:45) > this addresses the client side of device tree based clock lookups -> = - +> > add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu, viu, > mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the shared > mpc5121.dtsi include -> = - +> > these specs map 'clock-names' encoded in drivers to their respective > 'struct clk' items in the platform's clock driver -> = - +> > Signed-off-by: Gerhard Sittig <gsi@denx.de> Reviewed-by: Mike Turquette <mturquette@linaro.org> > --- -> arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++= -++++++ +> arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) -> = - -> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/m= -pc5121.dtsi +> +> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi > index 8f4cba0..3657ae6 100644 > --- a/arch/powerpc/boot/dts/mpc5121.dtsi > +++ b/arch/powerpc/boot/dts/mpc5121.dtsi > @@ -51,6 +51,10 @@ -> compatible =3D "fsl,mpc5121-mbx"; -> reg =3D <0x20000000 0x4000>; -> interrupts =3D <66 0x8>; -> + clocks =3D <&clks MPC512x_CLK_MBX_BUS>, +> compatible = "fsl,mpc5121-mbx"; +> reg = <0x20000000 0x4000>; +> interrupts = <66 0x8>; +> + clocks = <&clks MPC512x_CLK_MBX_BUS>, > + <&clks MPC512x_CLK_MBX_3D>, > + <&clks MPC512x_CLK_MBX>; -> + clock-names =3D "mbx-bus", "mbx-3d", "mbx"; +> + clock-names = "mbx-bus", "mbx-3d", "mbx"; > }; -> = - -> sram@30000000 { +> +> sram at 30000000 { > @@ -64,6 +68,8 @@ -> interrupts =3D <6 8>; -> #address-cells =3D <1>; -> #size-cells =3D <1>; -> + clocks =3D <&clks MPC512x_CLK_NFC>; -> + clock-names =3D "per"; +> interrupts = <6 8>; +> #address-cells = <1>; +> #size-cells = <1>; +> + clocks = <&clks MPC512x_CLK_NFC>; +> + clock-names = "per"; > }; -> = - -> localbus@80000020 { +> +> localbus at 80000020 { > @@ -153,12 +159,22 @@ -> compatible =3D "fsl,mpc5121-mscan"; -> reg =3D <0x1300 0x80>; -> interrupts =3D <12 0x8>; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> compatible = "fsl,mpc5121-mscan"; +> reg = <0x1300 0x80>; +> interrupts = <12 0x8>; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SYS>, > + <&clks MPC512x_CLK_REF>, > + <&clks MPC512x_CLK_MSCAN0_MCLK>; -> + clock-names =3D "ips", "sys", "ref", "mclk"; +> + clock-names = "ips", "sys", "ref", "mclk"; > }; -> = - -> can@1380 { -> compatible =3D "fsl,mpc5121-mscan"; -> reg =3D <0x1380 0x80>; -> interrupts =3D <13 0x8>; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> +> can at 1380 { +> compatible = "fsl,mpc5121-mscan"; +> reg = <0x1380 0x80>; +> interrupts = <13 0x8>; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SYS>, > + <&clks MPC512x_CLK_REF>, > + <&clks MPC512x_CLK_MSCAN1_MCLK>; -> + clock-names =3D "ips", "sys", "ref", "mclk"; +> + clock-names = "ips", "sys", "ref", "mclk"; > }; -> = - -> sdhc@1500 { +> +> sdhc at 1500 { > @@ -167,6 +183,9 @@ -> interrupts =3D <8 0x8>; -> dmas =3D <&dma0 30>; -> dma-names =3D "rx-tx"; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> interrupts = <8 0x8>; +> dmas = <&dma0 30>; +> dma-names = "rx-tx"; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SDHC>; -> + clock-names =3D "ipg", "per"; +> + clock-names = "ipg", "per"; > }; -> = - -> i2c@1700 { +> +> i2c at 1700 { > @@ -175,6 +194,8 @@ -> compatible =3D "fsl,mpc5121-i2c", "fsl-i2c"; -> reg =3D <0x1700 0x20>; -> interrupts =3D <9 0x8>; -> + clocks =3D <&clks MPC512x_CLK_I2C>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +> reg = <0x1700 0x20>; +> interrupts = <9 0x8>; +> + clocks = <&clks MPC512x_CLK_I2C>; +> + clock-names = "per"; > }; -> = - -> i2c@1720 { +> +> i2c at 1720 { > @@ -183,6 +204,8 @@ -> compatible =3D "fsl,mpc5121-i2c", "fsl-i2c"; -> reg =3D <0x1720 0x20>; -> interrupts =3D <10 0x8>; -> + clocks =3D <&clks MPC512x_CLK_I2C>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +> reg = <0x1720 0x20>; +> interrupts = <10 0x8>; +> + clocks = <&clks MPC512x_CLK_I2C>; +> + clock-names = "per"; > }; -> = - -> i2c@1740 { +> +> i2c at 1740 { > @@ -191,6 +214,8 @@ -> compatible =3D "fsl,mpc5121-i2c", "fsl-i2c"; -> reg =3D <0x1740 0x20>; -> interrupts =3D <11 0x8>; -> + clocks =3D <&clks MPC512x_CLK_I2C>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +> reg = <0x1740 0x20>; +> interrupts = <11 0x8>; +> + clocks = <&clks MPC512x_CLK_I2C>; +> + clock-names = "per"; > }; -> = - -> i2ccontrol@1760 { +> +> i2ccontrol at 1760 { > @@ -202,30 +227,46 @@ -> compatible =3D "fsl,mpc5121-axe"; -> reg =3D <0x2000 0x100>; -> interrupts =3D <42 0x8>; -> + clocks =3D <&clks MPC512x_CLK_AXE>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-axe"; +> reg = <0x2000 0x100>; +> interrupts = <42 0x8>; +> + clocks = <&clks MPC512x_CLK_AXE>; +> + clock-names = "per"; > }; -> = - -> display@2100 { -> compatible =3D "fsl,mpc5121-diu"; -> reg =3D <0x2100 0x100>; -> interrupts =3D <64 0x8>; -> + clocks =3D <&clks MPC512x_CLK_DIU>; -> + clock-names =3D "per"; +> +> display at 2100 { +> compatible = "fsl,mpc5121-diu"; +> reg = <0x2100 0x100>; +> interrupts = <64 0x8>; +> + clocks = <&clks MPC512x_CLK_DIU>; +> + clock-names = "per"; > }; -> = - -> can@2300 { -> compatible =3D "fsl,mpc5121-mscan"; -> reg =3D <0x2300 0x80>; -> interrupts =3D <90 0x8>; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> +> can at 2300 { +> compatible = "fsl,mpc5121-mscan"; +> reg = <0x2300 0x80>; +> interrupts = <90 0x8>; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SYS>, > + <&clks MPC512x_CLK_REF>, > + <&clks MPC512x_CLK_MSCAN2_MCLK>; -> + clock-names =3D "ips", "sys", "ref", "mclk"; +> + clock-names = "ips", "sys", "ref", "mclk"; > }; -> = - -> can@2380 { -> compatible =3D "fsl,mpc5121-mscan"; -> reg =3D <0x2380 0x80>; -> interrupts =3D <91 0x8>; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> +> can at 2380 { +> compatible = "fsl,mpc5121-mscan"; +> reg = <0x2380 0x80>; +> interrupts = <91 0x8>; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SYS>, > + <&clks MPC512x_CLK_REF>, > + <&clks MPC512x_CLK_MSCAN3_MCLK>; -> + clock-names =3D "ips", "sys", "ref", "mclk"; +> + clock-names = "ips", "sys", "ref", "mclk"; > }; -> = - -> viu@2400 { -> compatible =3D "fsl,mpc5121-viu"; -> reg =3D <0x2400 0x400>; -> interrupts =3D <67 0x8>; -> + clocks =3D <&clks MPC512x_CLK_VIU>; -> + clock-names =3D "per"; +> +> viu at 2400 { +> compatible = "fsl,mpc5121-viu"; +> reg = <0x2400 0x400>; +> interrupts = <67 0x8>; +> + clocks = <&clks MPC512x_CLK_VIU>; +> + clock-names = "per"; > }; -> = - -> mdio@2800 { +> +> mdio at 2800 { > @@ -233,6 +274,8 @@ -> reg =3D <0x2800 0x800>; -> #address-cells =3D <1>; -> #size-cells =3D <0>; -> + clocks =3D <&clks MPC512x_CLK_FEC>; -> + clock-names =3D "per"; +> reg = <0x2800 0x800>; +> #address-cells = <1>; +> #size-cells = <0>; +> + clocks = <&clks MPC512x_CLK_FEC>; +> + clock-names = "per"; > }; -> = - -> eth0: ethernet@2800 { +> +> eth0: ethernet at 2800 { > @@ -241,6 +284,8 @@ -> reg =3D <0x2800 0x800>; -> local-mac-address =3D [ 00 00 00 00 00 00 ]; -> interrupts =3D <4 0x8>; -> + clocks =3D <&clks MPC512x_CLK_FEC>; -> + clock-names =3D "per"; +> reg = <0x2800 0x800>; +> local-mac-address = [ 00 00 00 00 00 00 ]; +> interrupts = <4 0x8>; +> + clocks = <&clks MPC512x_CLK_FEC>; +> + clock-names = "per"; > }; -> = - +> > /* USB1 using external ULPI PHY */ > @@ -252,6 +297,8 @@ -> interrupts =3D <43 0x8>; -> dr_mode =3D "otg"; -> phy_type =3D "ulpi"; -> + clocks =3D <&clks MPC512x_CLK_USB1>; -> + clock-names =3D "per"; +> interrupts = <43 0x8>; +> dr_mode = "otg"; +> phy_type = "ulpi"; +> + clocks = <&clks MPC512x_CLK_USB1>; +> + clock-names = "per"; > }; -> = - +> > /* USB0 using internal UTMI PHY */ > @@ -263,6 +310,8 @@ -> interrupts =3D <44 0x8>; -> dr_mode =3D "otg"; -> phy_type =3D "utmi_wide"; -> + clocks =3D <&clks MPC512x_CLK_USB2>; -> + clock-names =3D "per"; +> interrupts = <44 0x8>; +> dr_mode = "otg"; +> phy_type = "utmi_wide"; +> + clocks = <&clks MPC512x_CLK_USB2>; +> + clock-names = "per"; > }; -> = - +> > /* IO control */ > @@ -281,6 +330,8 @@ -> compatible =3D "fsl,mpc5121-pata"; -> reg =3D <0x10200 0x100>; -> interrupts =3D <5 0x8>; -> + clocks =3D <&clks MPC512x_CLK_PATA>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-pata"; +> reg = <0x10200 0x100>; +> interrupts = <5 0x8>; +> + clocks = <&clks MPC512x_CLK_PATA>; +> + clock-names = "per"; > }; -> = - +> > /* 512x PSCs are not 52xx PSC compatible */ > @@ -292,6 +343,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC0_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC0_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC1 */ > @@ -301,6 +354,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC1_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC1_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC2 */ > @@ -310,6 +365,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC2_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC2_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC3 */ > @@ -319,6 +376,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC3_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC3_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC4 */ > @@ -328,6 +387,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC4_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC4_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC5 */ > @@ -337,6 +398,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC5_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC5_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC6 */ > @@ -346,6 +409,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC6_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC6_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC7 */ > @@ -355,6 +420,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC7_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC7_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC8 */ > @@ -364,6 +431,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC8_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC8_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC9 */ > @@ -373,6 +442,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC9_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC9_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC10 */ > @@ -382,6 +453,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC10_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC10_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC11 */ > @@ -391,12 +464,16 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC11_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC11_MCLK>; +> + clock-names = "mclk"; > }; -> = - -> pscfifo@11f00 { -> compatible =3D "fsl,mpc5121-psc-fifo"; -> reg =3D <0x11f00 0x100>; -> interrupts =3D <40 0x8>; -> + clocks =3D <&clks MPC512x_CLK_PSC_FIFO>; -> + clock-names =3D "per"; +> +> pscfifo at 11f00 { +> compatible = "fsl,mpc5121-psc-fifo"; +> reg = <0x11f00 0x100>; +> interrupts = <40 0x8>; +> + clocks = <&clks MPC512x_CLK_PSC_FIFO>; +> + clock-names = "per"; > }; -> = - -> dma0: dma@14000 { +> +> dma0: dma at 14000 { > @@ -414,6 +491,8 @@ -> #address-cells =3D <3>; -> #size-cells =3D <2>; -> #interrupt-cells =3D <1>; -> + clocks =3D <&clks MPC512x_CLK_PCI>; -> + clock-names =3D "per"; -> = - -> reg =3D <0x80008500 0x100 /* internal registers */ -> 0x80008300 0x8>; /* config space access registers = -*/ -> -- = - +> #address-cells = <3>; +> #size-cells = <2>; +> #interrupt-cells = <1>; +> + clocks = <&clks MPC512x_CLK_PCI>; +> + clock-names = "per"; +> +> reg = <0x80008500 0x100 /* internal registers */ +> 0x80008300 0x8>; /* config space access registers */ +> -- > 1.7.10.4 diff --git a/a/content_digest b/N1/content_digest index 0977dd9..a4c9c10 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,386 +1,332 @@ "ref\01374166855-7280-1-git-send-email-gsi@denx.de\0" "ref\01374495298-22019-1-git-send-email-gsi@denx.de\0" "ref\01374495298-22019-19-git-send-email-gsi@denx.de\0" - "From\0Mike Turquette <mturquette@linaro.org>\0" - "Subject\0Re: [PATCH v3 18/31] dts: mpc512x: add clock specs for client lookups\0" + "From\0mturquette@linaro.org (Mike Turquette)\0" + "Subject\0[PATCH v3 18/31] dts: mpc512x: add clock specs for client lookups\0" "Date\0Fri, 02 Aug 2013 16:41:20 -0700\0" - "To\0Gerhard Sittig <gsi@denx.de>" - linuxppc-dev@lists.ozlabs.org - Anatolij Gustschin <agust@denx.de> - linux-arm-kernel@lists.infradead.org - " devicetree-discuss@lists.ozlabs.org\0" - "Cc\0Detlev Zundel <dzu@denx.de>" - Wolfram Sang <wsa@the-dreams.de> - Greg Kroah-Hartman <gregkh@linuxfoundation.org> - Gerhard Sittig <gsi@denx.de> - Rob Herring <rob.herring@calxeda.com> - Mark Brown <broonie@kernel.org> - Marc Kleine-Budde <mkl@pengutronix.de> - David Woodhouse <dwmw2@infradead.org> - Wolfgang Grandegger <wg@grandegger.com> - " Mauro Carvalho Chehab <m.chehab@samsung.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Gerhard Sittig (2013-07-22 05:14:45)\n" "> this addresses the client side of device tree based clock lookups\n" - "> =\n" - "\n" + "> \n" "> add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu, viu,\n" "> mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the shared\n" "> mpc5121.dtsi include\n" - "> =\n" - "\n" + "> \n" "> these specs map 'clock-names' encoded in drivers to their respective\n" "> 'struct clk' items in the platform's clock driver\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Gerhard Sittig <gsi@denx.de>\n" "\n" "Reviewed-by: Mike Turquette <mturquette@linaro.org>\n" "\n" "> ---\n" - "> arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 79 insertions(+)\n" - "> =\n" - "\n" - "> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/m=\n" - "pc5121.dtsi\n" + "> \n" + "> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi\n" "> index 8f4cba0..3657ae6 100644\n" "> --- a/arch/powerpc/boot/dts/mpc5121.dtsi\n" "> +++ b/arch/powerpc/boot/dts/mpc5121.dtsi\n" "> @@ -51,6 +51,10 @@\n" - "> compatible =3D \"fsl,mpc5121-mbx\";\n" - "> reg =3D <0x20000000 0x4000>;\n" - "> interrupts =3D <66 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_MBX_BUS>,\n" + "> compatible = \"fsl,mpc5121-mbx\";\n" + "> reg = <0x20000000 0x4000>;\n" + "> interrupts = <66 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_MBX_BUS>,\n" "> + <&clks MPC512x_CLK_MBX_3D>,\n" "> + <&clks MPC512x_CLK_MBX>;\n" - "> + clock-names =3D \"mbx-bus\", \"mbx-3d\", \"mbx\";\n" + "> + clock-names = \"mbx-bus\", \"mbx-3d\", \"mbx\";\n" "> };\n" - "> =\n" - "\n" - "> sram@30000000 {\n" + "> \n" + "> sram at 30000000 {\n" "> @@ -64,6 +68,8 @@\n" - "> interrupts =3D <6 8>;\n" - "> #address-cells =3D <1>;\n" - "> #size-cells =3D <1>;\n" - "> + clocks =3D <&clks MPC512x_CLK_NFC>;\n" - "> + clock-names =3D \"per\";\n" + "> interrupts = <6 8>;\n" + "> #address-cells = <1>;\n" + "> #size-cells = <1>;\n" + "> + clocks = <&clks MPC512x_CLK_NFC>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" - "> localbus@80000020 {\n" + "> \n" + "> localbus at 80000020 {\n" "> @@ -153,12 +159,22 @@\n" - "> compatible =3D \"fsl,mpc5121-mscan\";\n" - "> reg =3D <0x1300 0x80>;\n" - "> interrupts =3D <12 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> compatible = \"fsl,mpc5121-mscan\";\n" + "> reg = <0x1300 0x80>;\n" + "> interrupts = <12 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SYS>,\n" "> + <&clks MPC512x_CLK_REF>,\n" "> + <&clks MPC512x_CLK_MSCAN0_MCLK>;\n" - "> + clock-names =3D \"ips\", \"sys\", \"ref\", \"mclk\";\n" + "> + clock-names = \"ips\", \"sys\", \"ref\", \"mclk\";\n" "> };\n" - "> =\n" - "\n" - "> can@1380 {\n" - "> compatible =3D \"fsl,mpc5121-mscan\";\n" - "> reg =3D <0x1380 0x80>;\n" - "> interrupts =3D <13 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> \n" + "> can at 1380 {\n" + "> compatible = \"fsl,mpc5121-mscan\";\n" + "> reg = <0x1380 0x80>;\n" + "> interrupts = <13 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SYS>,\n" "> + <&clks MPC512x_CLK_REF>,\n" "> + <&clks MPC512x_CLK_MSCAN1_MCLK>;\n" - "> + clock-names =3D \"ips\", \"sys\", \"ref\", \"mclk\";\n" + "> + clock-names = \"ips\", \"sys\", \"ref\", \"mclk\";\n" "> };\n" - "> =\n" - "\n" - "> sdhc@1500 {\n" + "> \n" + "> sdhc at 1500 {\n" "> @@ -167,6 +183,9 @@\n" - "> interrupts =3D <8 0x8>;\n" - "> dmas =3D <&dma0 30>;\n" - "> dma-names =3D \"rx-tx\";\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> interrupts = <8 0x8>;\n" + "> dmas = <&dma0 30>;\n" + "> dma-names = \"rx-tx\";\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SDHC>;\n" - "> + clock-names =3D \"ipg\", \"per\";\n" + "> + clock-names = \"ipg\", \"per\";\n" "> };\n" - "> =\n" - "\n" - "> i2c@1700 {\n" + "> \n" + "> i2c at 1700 {\n" "> @@ -175,6 +194,8 @@\n" - "> compatible =3D \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" - "> reg =3D <0x1700 0x20>;\n" - "> interrupts =3D <9 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_I2C>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" + "> reg = <0x1700 0x20>;\n" + "> interrupts = <9 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_I2C>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" - "> i2c@1720 {\n" + "> \n" + "> i2c at 1720 {\n" "> @@ -183,6 +204,8 @@\n" - "> compatible =3D \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" - "> reg =3D <0x1720 0x20>;\n" - "> interrupts =3D <10 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_I2C>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" + "> reg = <0x1720 0x20>;\n" + "> interrupts = <10 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_I2C>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" - "> i2c@1740 {\n" + "> \n" + "> i2c at 1740 {\n" "> @@ -191,6 +214,8 @@\n" - "> compatible =3D \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" - "> reg =3D <0x1740 0x20>;\n" - "> interrupts =3D <11 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_I2C>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" + "> reg = <0x1740 0x20>;\n" + "> interrupts = <11 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_I2C>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" - "> i2ccontrol@1760 {\n" + "> \n" + "> i2ccontrol at 1760 {\n" "> @@ -202,30 +227,46 @@\n" - "> compatible =3D \"fsl,mpc5121-axe\";\n" - "> reg =3D <0x2000 0x100>;\n" - "> interrupts =3D <42 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_AXE>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-axe\";\n" + "> reg = <0x2000 0x100>;\n" + "> interrupts = <42 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_AXE>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" - "> display@2100 {\n" - "> compatible =3D \"fsl,mpc5121-diu\";\n" - "> reg =3D <0x2100 0x100>;\n" - "> interrupts =3D <64 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_DIU>;\n" - "> + clock-names =3D \"per\";\n" + "> \n" + "> display at 2100 {\n" + "> compatible = \"fsl,mpc5121-diu\";\n" + "> reg = <0x2100 0x100>;\n" + "> interrupts = <64 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_DIU>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" - "> can@2300 {\n" - "> compatible =3D \"fsl,mpc5121-mscan\";\n" - "> reg =3D <0x2300 0x80>;\n" - "> interrupts =3D <90 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> \n" + "> can at 2300 {\n" + "> compatible = \"fsl,mpc5121-mscan\";\n" + "> reg = <0x2300 0x80>;\n" + "> interrupts = <90 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SYS>,\n" "> + <&clks MPC512x_CLK_REF>,\n" "> + <&clks MPC512x_CLK_MSCAN2_MCLK>;\n" - "> + clock-names =3D \"ips\", \"sys\", \"ref\", \"mclk\";\n" + "> + clock-names = \"ips\", \"sys\", \"ref\", \"mclk\";\n" "> };\n" - "> =\n" - "\n" - "> can@2380 {\n" - "> compatible =3D \"fsl,mpc5121-mscan\";\n" - "> reg =3D <0x2380 0x80>;\n" - "> interrupts =3D <91 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> \n" + "> can at 2380 {\n" + "> compatible = \"fsl,mpc5121-mscan\";\n" + "> reg = <0x2380 0x80>;\n" + "> interrupts = <91 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SYS>,\n" "> + <&clks MPC512x_CLK_REF>,\n" "> + <&clks MPC512x_CLK_MSCAN3_MCLK>;\n" - "> + clock-names =3D \"ips\", \"sys\", \"ref\", \"mclk\";\n" + "> + clock-names = \"ips\", \"sys\", \"ref\", \"mclk\";\n" "> };\n" - "> =\n" - "\n" - "> viu@2400 {\n" - "> compatible =3D \"fsl,mpc5121-viu\";\n" - "> reg =3D <0x2400 0x400>;\n" - "> interrupts =3D <67 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_VIU>;\n" - "> + clock-names =3D \"per\";\n" + "> \n" + "> viu at 2400 {\n" + "> compatible = \"fsl,mpc5121-viu\";\n" + "> reg = <0x2400 0x400>;\n" + "> interrupts = <67 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_VIU>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" - "> mdio@2800 {\n" + "> \n" + "> mdio at 2800 {\n" "> @@ -233,6 +274,8 @@\n" - "> reg =3D <0x2800 0x800>;\n" - "> #address-cells =3D <1>;\n" - "> #size-cells =3D <0>;\n" - "> + clocks =3D <&clks MPC512x_CLK_FEC>;\n" - "> + clock-names =3D \"per\";\n" + "> reg = <0x2800 0x800>;\n" + "> #address-cells = <1>;\n" + "> #size-cells = <0>;\n" + "> + clocks = <&clks MPC512x_CLK_FEC>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" - "> eth0: ethernet@2800 {\n" + "> \n" + "> eth0: ethernet at 2800 {\n" "> @@ -241,6 +284,8 @@\n" - "> reg =3D <0x2800 0x800>;\n" - "> local-mac-address =3D [ 00 00 00 00 00 00 ];\n" - "> interrupts =3D <4 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_FEC>;\n" - "> + clock-names =3D \"per\";\n" + "> reg = <0x2800 0x800>;\n" + "> local-mac-address = [ 00 00 00 00 00 00 ];\n" + "> interrupts = <4 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_FEC>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* USB1 using external ULPI PHY */\n" "> @@ -252,6 +297,8 @@\n" - "> interrupts =3D <43 0x8>;\n" - "> dr_mode =3D \"otg\";\n" - "> phy_type =3D \"ulpi\";\n" - "> + clocks =3D <&clks MPC512x_CLK_USB1>;\n" - "> + clock-names =3D \"per\";\n" + "> interrupts = <43 0x8>;\n" + "> dr_mode = \"otg\";\n" + "> phy_type = \"ulpi\";\n" + "> + clocks = <&clks MPC512x_CLK_USB1>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* USB0 using internal UTMI PHY */\n" "> @@ -263,6 +310,8 @@\n" - "> interrupts =3D <44 0x8>;\n" - "> dr_mode =3D \"otg\";\n" - "> phy_type =3D \"utmi_wide\";\n" - "> + clocks =3D <&clks MPC512x_CLK_USB2>;\n" - "> + clock-names =3D \"per\";\n" + "> interrupts = <44 0x8>;\n" + "> dr_mode = \"otg\";\n" + "> phy_type = \"utmi_wide\";\n" + "> + clocks = <&clks MPC512x_CLK_USB2>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* IO control */\n" "> @@ -281,6 +330,8 @@\n" - "> compatible =3D \"fsl,mpc5121-pata\";\n" - "> reg =3D <0x10200 0x100>;\n" - "> interrupts =3D <5 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PATA>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-pata\";\n" + "> reg = <0x10200 0x100>;\n" + "> interrupts = <5 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_PATA>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* 512x PSCs are not 52xx PSC compatible */\n" "> @@ -292,6 +343,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC0_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC0_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC1 */\n" "> @@ -301,6 +354,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC1_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC1_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC2 */\n" "> @@ -310,6 +365,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC2_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC2_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC3 */\n" "> @@ -319,6 +376,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC3_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC3_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC4 */\n" "> @@ -328,6 +387,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC4_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC4_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC5 */\n" "> @@ -337,6 +398,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC5_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC5_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC6 */\n" "> @@ -346,6 +409,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC6_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC6_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC7 */\n" "> @@ -355,6 +420,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC7_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC7_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC8 */\n" "> @@ -364,6 +431,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC8_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC8_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC9 */\n" "> @@ -373,6 +442,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC9_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC9_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC10 */\n" "> @@ -382,6 +453,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC10_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC10_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC11 */\n" "> @@ -391,12 +464,16 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC11_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC11_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" - "> pscfifo@11f00 {\n" - "> compatible =3D \"fsl,mpc5121-psc-fifo\";\n" - "> reg =3D <0x11f00 0x100>;\n" - "> interrupts =3D <40 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC_FIFO>;\n" - "> + clock-names =3D \"per\";\n" + "> \n" + "> pscfifo at 11f00 {\n" + "> compatible = \"fsl,mpc5121-psc-fifo\";\n" + "> reg = <0x11f00 0x100>;\n" + "> interrupts = <40 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC_FIFO>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" - "> dma0: dma@14000 {\n" + "> \n" + "> dma0: dma at 14000 {\n" "> @@ -414,6 +491,8 @@\n" - "> #address-cells =3D <3>;\n" - "> #size-cells =3D <2>;\n" - "> #interrupt-cells =3D <1>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PCI>;\n" - "> + clock-names =3D \"per\";\n" - "> =\n" - "\n" - "> reg =3D <0x80008500 0x100 /* internal registers */\n" - "> 0x80008300 0x8>; /* config space access registers =\n" - "*/\n" - "> -- =\n" - "\n" + "> #address-cells = <3>;\n" + "> #size-cells = <2>;\n" + "> #interrupt-cells = <1>;\n" + "> + clocks = <&clks MPC512x_CLK_PCI>;\n" + "> + clock-names = \"per\";\n" + "> \n" + "> reg = <0x80008500 0x100 /* internal registers */\n" + "> 0x80008300 0x8>; /* config space access registers */\n" + "> -- \n" > 1.7.10.4 -d8fa1c964180e3fc3cd43575e95b1b8e6518c4496d531e0175c9270d580e2547 +b5e079db3efb5a7438d1bfcce9b1cc60324eb450954c3f0d03c9ef123c4a6f4b
diff --git a/a/1.txt b/N2/1.txt index 794c672..db86f39 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,361 +1,321 @@ Quoting Gerhard Sittig (2013-07-22 05:14:45) > this addresses the client side of device tree based clock lookups -> = - +> > add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu, viu, > mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the shared > mpc5121.dtsi include -> = - +> > these specs map 'clock-names' encoded in drivers to their respective > 'struct clk' items in the platform's clock driver -> = - +> > Signed-off-by: Gerhard Sittig <gsi@denx.de> Reviewed-by: Mike Turquette <mturquette@linaro.org> > --- -> arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++= -++++++ +> arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) -> = - -> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/m= -pc5121.dtsi +> +> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi > index 8f4cba0..3657ae6 100644 > --- a/arch/powerpc/boot/dts/mpc5121.dtsi > +++ b/arch/powerpc/boot/dts/mpc5121.dtsi > @@ -51,6 +51,10 @@ -> compatible =3D "fsl,mpc5121-mbx"; -> reg =3D <0x20000000 0x4000>; -> interrupts =3D <66 0x8>; -> + clocks =3D <&clks MPC512x_CLK_MBX_BUS>, +> compatible = "fsl,mpc5121-mbx"; +> reg = <0x20000000 0x4000>; +> interrupts = <66 0x8>; +> + clocks = <&clks MPC512x_CLK_MBX_BUS>, > + <&clks MPC512x_CLK_MBX_3D>, > + <&clks MPC512x_CLK_MBX>; -> + clock-names =3D "mbx-bus", "mbx-3d", "mbx"; +> + clock-names = "mbx-bus", "mbx-3d", "mbx"; > }; -> = - +> > sram@30000000 { > @@ -64,6 +68,8 @@ -> interrupts =3D <6 8>; -> #address-cells =3D <1>; -> #size-cells =3D <1>; -> + clocks =3D <&clks MPC512x_CLK_NFC>; -> + clock-names =3D "per"; +> interrupts = <6 8>; +> #address-cells = <1>; +> #size-cells = <1>; +> + clocks = <&clks MPC512x_CLK_NFC>; +> + clock-names = "per"; > }; -> = - +> > localbus@80000020 { > @@ -153,12 +159,22 @@ -> compatible =3D "fsl,mpc5121-mscan"; -> reg =3D <0x1300 0x80>; -> interrupts =3D <12 0x8>; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> compatible = "fsl,mpc5121-mscan"; +> reg = <0x1300 0x80>; +> interrupts = <12 0x8>; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SYS>, > + <&clks MPC512x_CLK_REF>, > + <&clks MPC512x_CLK_MSCAN0_MCLK>; -> + clock-names =3D "ips", "sys", "ref", "mclk"; +> + clock-names = "ips", "sys", "ref", "mclk"; > }; -> = - +> > can@1380 { -> compatible =3D "fsl,mpc5121-mscan"; -> reg =3D <0x1380 0x80>; -> interrupts =3D <13 0x8>; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> compatible = "fsl,mpc5121-mscan"; +> reg = <0x1380 0x80>; +> interrupts = <13 0x8>; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SYS>, > + <&clks MPC512x_CLK_REF>, > + <&clks MPC512x_CLK_MSCAN1_MCLK>; -> + clock-names =3D "ips", "sys", "ref", "mclk"; +> + clock-names = "ips", "sys", "ref", "mclk"; > }; -> = - +> > sdhc@1500 { > @@ -167,6 +183,9 @@ -> interrupts =3D <8 0x8>; -> dmas =3D <&dma0 30>; -> dma-names =3D "rx-tx"; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> interrupts = <8 0x8>; +> dmas = <&dma0 30>; +> dma-names = "rx-tx"; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SDHC>; -> + clock-names =3D "ipg", "per"; +> + clock-names = "ipg", "per"; > }; -> = - +> > i2c@1700 { > @@ -175,6 +194,8 @@ -> compatible =3D "fsl,mpc5121-i2c", "fsl-i2c"; -> reg =3D <0x1700 0x20>; -> interrupts =3D <9 0x8>; -> + clocks =3D <&clks MPC512x_CLK_I2C>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +> reg = <0x1700 0x20>; +> interrupts = <9 0x8>; +> + clocks = <&clks MPC512x_CLK_I2C>; +> + clock-names = "per"; > }; -> = - +> > i2c@1720 { > @@ -183,6 +204,8 @@ -> compatible =3D "fsl,mpc5121-i2c", "fsl-i2c"; -> reg =3D <0x1720 0x20>; -> interrupts =3D <10 0x8>; -> + clocks =3D <&clks MPC512x_CLK_I2C>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +> reg = <0x1720 0x20>; +> interrupts = <10 0x8>; +> + clocks = <&clks MPC512x_CLK_I2C>; +> + clock-names = "per"; > }; -> = - +> > i2c@1740 { > @@ -191,6 +214,8 @@ -> compatible =3D "fsl,mpc5121-i2c", "fsl-i2c"; -> reg =3D <0x1740 0x20>; -> interrupts =3D <11 0x8>; -> + clocks =3D <&clks MPC512x_CLK_I2C>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-i2c", "fsl-i2c"; +> reg = <0x1740 0x20>; +> interrupts = <11 0x8>; +> + clocks = <&clks MPC512x_CLK_I2C>; +> + clock-names = "per"; > }; -> = - +> > i2ccontrol@1760 { > @@ -202,30 +227,46 @@ -> compatible =3D "fsl,mpc5121-axe"; -> reg =3D <0x2000 0x100>; -> interrupts =3D <42 0x8>; -> + clocks =3D <&clks MPC512x_CLK_AXE>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-axe"; +> reg = <0x2000 0x100>; +> interrupts = <42 0x8>; +> + clocks = <&clks MPC512x_CLK_AXE>; +> + clock-names = "per"; > }; -> = - +> > display@2100 { -> compatible =3D "fsl,mpc5121-diu"; -> reg =3D <0x2100 0x100>; -> interrupts =3D <64 0x8>; -> + clocks =3D <&clks MPC512x_CLK_DIU>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-diu"; +> reg = <0x2100 0x100>; +> interrupts = <64 0x8>; +> + clocks = <&clks MPC512x_CLK_DIU>; +> + clock-names = "per"; > }; -> = - +> > can@2300 { -> compatible =3D "fsl,mpc5121-mscan"; -> reg =3D <0x2300 0x80>; -> interrupts =3D <90 0x8>; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> compatible = "fsl,mpc5121-mscan"; +> reg = <0x2300 0x80>; +> interrupts = <90 0x8>; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SYS>, > + <&clks MPC512x_CLK_REF>, > + <&clks MPC512x_CLK_MSCAN2_MCLK>; -> + clock-names =3D "ips", "sys", "ref", "mclk"; +> + clock-names = "ips", "sys", "ref", "mclk"; > }; -> = - +> > can@2380 { -> compatible =3D "fsl,mpc5121-mscan"; -> reg =3D <0x2380 0x80>; -> interrupts =3D <91 0x8>; -> + clocks =3D <&clks MPC512x_CLK_IPS>, +> compatible = "fsl,mpc5121-mscan"; +> reg = <0x2380 0x80>; +> interrupts = <91 0x8>; +> + clocks = <&clks MPC512x_CLK_IPS>, > + <&clks MPC512x_CLK_SYS>, > + <&clks MPC512x_CLK_REF>, > + <&clks MPC512x_CLK_MSCAN3_MCLK>; -> + clock-names =3D "ips", "sys", "ref", "mclk"; +> + clock-names = "ips", "sys", "ref", "mclk"; > }; -> = - +> > viu@2400 { -> compatible =3D "fsl,mpc5121-viu"; -> reg =3D <0x2400 0x400>; -> interrupts =3D <67 0x8>; -> + clocks =3D <&clks MPC512x_CLK_VIU>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-viu"; +> reg = <0x2400 0x400>; +> interrupts = <67 0x8>; +> + clocks = <&clks MPC512x_CLK_VIU>; +> + clock-names = "per"; > }; -> = - +> > mdio@2800 { > @@ -233,6 +274,8 @@ -> reg =3D <0x2800 0x800>; -> #address-cells =3D <1>; -> #size-cells =3D <0>; -> + clocks =3D <&clks MPC512x_CLK_FEC>; -> + clock-names =3D "per"; +> reg = <0x2800 0x800>; +> #address-cells = <1>; +> #size-cells = <0>; +> + clocks = <&clks MPC512x_CLK_FEC>; +> + clock-names = "per"; > }; -> = - +> > eth0: ethernet@2800 { > @@ -241,6 +284,8 @@ -> reg =3D <0x2800 0x800>; -> local-mac-address =3D [ 00 00 00 00 00 00 ]; -> interrupts =3D <4 0x8>; -> + clocks =3D <&clks MPC512x_CLK_FEC>; -> + clock-names =3D "per"; +> reg = <0x2800 0x800>; +> local-mac-address = [ 00 00 00 00 00 00 ]; +> interrupts = <4 0x8>; +> + clocks = <&clks MPC512x_CLK_FEC>; +> + clock-names = "per"; > }; -> = - +> > /* USB1 using external ULPI PHY */ > @@ -252,6 +297,8 @@ -> interrupts =3D <43 0x8>; -> dr_mode =3D "otg"; -> phy_type =3D "ulpi"; -> + clocks =3D <&clks MPC512x_CLK_USB1>; -> + clock-names =3D "per"; +> interrupts = <43 0x8>; +> dr_mode = "otg"; +> phy_type = "ulpi"; +> + clocks = <&clks MPC512x_CLK_USB1>; +> + clock-names = "per"; > }; -> = - +> > /* USB0 using internal UTMI PHY */ > @@ -263,6 +310,8 @@ -> interrupts =3D <44 0x8>; -> dr_mode =3D "otg"; -> phy_type =3D "utmi_wide"; -> + clocks =3D <&clks MPC512x_CLK_USB2>; -> + clock-names =3D "per"; +> interrupts = <44 0x8>; +> dr_mode = "otg"; +> phy_type = "utmi_wide"; +> + clocks = <&clks MPC512x_CLK_USB2>; +> + clock-names = "per"; > }; -> = - +> > /* IO control */ > @@ -281,6 +330,8 @@ -> compatible =3D "fsl,mpc5121-pata"; -> reg =3D <0x10200 0x100>; -> interrupts =3D <5 0x8>; -> + clocks =3D <&clks MPC512x_CLK_PATA>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-pata"; +> reg = <0x10200 0x100>; +> interrupts = <5 0x8>; +> + clocks = <&clks MPC512x_CLK_PATA>; +> + clock-names = "per"; > }; -> = - +> > /* 512x PSCs are not 52xx PSC compatible */ > @@ -292,6 +343,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC0_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC0_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC1 */ > @@ -301,6 +354,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC1_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC1_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC2 */ > @@ -310,6 +365,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC2_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC2_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC3 */ > @@ -319,6 +376,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC3_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC3_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC4 */ > @@ -328,6 +387,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC4_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC4_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC5 */ > @@ -337,6 +398,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC5_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC5_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC6 */ > @@ -346,6 +409,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC6_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC6_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC7 */ > @@ -355,6 +420,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC7_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC7_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC8 */ > @@ -364,6 +431,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC8_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC8_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC9 */ > @@ -373,6 +442,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC9_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC9_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC10 */ > @@ -382,6 +453,8 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC10_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC10_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > /* PSC11 */ > @@ -391,12 +464,16 @@ -> interrupts =3D <40 0x8>; -> fsl,rx-fifo-size =3D <16>; -> fsl,tx-fifo-size =3D <16>; -> + clocks =3D <&clks MPC512x_CLK_PSC11_MCLK>; -> + clock-names =3D "mclk"; +> interrupts = <40 0x8>; +> fsl,rx-fifo-size = <16>; +> fsl,tx-fifo-size = <16>; +> + clocks = <&clks MPC512x_CLK_PSC11_MCLK>; +> + clock-names = "mclk"; > }; -> = - +> > pscfifo@11f00 { -> compatible =3D "fsl,mpc5121-psc-fifo"; -> reg =3D <0x11f00 0x100>; -> interrupts =3D <40 0x8>; -> + clocks =3D <&clks MPC512x_CLK_PSC_FIFO>; -> + clock-names =3D "per"; +> compatible = "fsl,mpc5121-psc-fifo"; +> reg = <0x11f00 0x100>; +> interrupts = <40 0x8>; +> + clocks = <&clks MPC512x_CLK_PSC_FIFO>; +> + clock-names = "per"; > }; -> = - +> > dma0: dma@14000 { > @@ -414,6 +491,8 @@ -> #address-cells =3D <3>; -> #size-cells =3D <2>; -> #interrupt-cells =3D <1>; -> + clocks =3D <&clks MPC512x_CLK_PCI>; -> + clock-names =3D "per"; -> = - -> reg =3D <0x80008500 0x100 /* internal registers */ -> 0x80008300 0x8>; /* config space access registers = -*/ -> -- = - +> #address-cells = <3>; +> #size-cells = <2>; +> #interrupt-cells = <1>; +> + clocks = <&clks MPC512x_CLK_PCI>; +> + clock-names = "per"; +> +> reg = <0x80008500 0x100 /* internal registers */ +> 0x80008300 0x8>; /* config space access registers */ +> -- > 1.7.10.4 diff --git a/a/content_digest b/N2/content_digest index 0977dd9..e358c56 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -4,8 +4,7 @@ "From\0Mike Turquette <mturquette@linaro.org>\0" "Subject\0Re: [PATCH v3 18/31] dts: mpc512x: add clock specs for client lookups\0" "Date\0Fri, 02 Aug 2013 16:41:20 -0700\0" - "To\0Gerhard Sittig <gsi@denx.de>" - linuxppc-dev@lists.ozlabs.org + "To\0linuxppc-dev@lists.ozlabs.org" Anatolij Gustschin <agust@denx.de> linux-arm-kernel@lists.infradead.org " devicetree-discuss@lists.ozlabs.org\0" @@ -23,364 +22,324 @@ "b\0" "Quoting Gerhard Sittig (2013-07-22 05:14:45)\n" "> this addresses the client side of device tree based clock lookups\n" - "> =\n" - "\n" + "> \n" "> add clock specifiers to the mbx, nfc, mscan, sdhc, i2c, axe, diu, viu,\n" "> mdio, fec, usb, pata, psc, psc fifo, and pci nodes in the shared\n" "> mpc5121.dtsi include\n" - "> =\n" - "\n" + "> \n" "> these specs map 'clock-names' encoded in drivers to their respective\n" "> 'struct clk' items in the platform's clock driver\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Gerhard Sittig <gsi@denx.de>\n" "\n" "Reviewed-by: Mike Turquette <mturquette@linaro.org>\n" "\n" "> ---\n" - "> arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> arch/powerpc/boot/dts/mpc5121.dtsi | 79 ++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 79 insertions(+)\n" - "> =\n" - "\n" - "> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/m=\n" - "pc5121.dtsi\n" + "> \n" + "> diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi\n" "> index 8f4cba0..3657ae6 100644\n" "> --- a/arch/powerpc/boot/dts/mpc5121.dtsi\n" "> +++ b/arch/powerpc/boot/dts/mpc5121.dtsi\n" "> @@ -51,6 +51,10 @@\n" - "> compatible =3D \"fsl,mpc5121-mbx\";\n" - "> reg =3D <0x20000000 0x4000>;\n" - "> interrupts =3D <66 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_MBX_BUS>,\n" + "> compatible = \"fsl,mpc5121-mbx\";\n" + "> reg = <0x20000000 0x4000>;\n" + "> interrupts = <66 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_MBX_BUS>,\n" "> + <&clks MPC512x_CLK_MBX_3D>,\n" "> + <&clks MPC512x_CLK_MBX>;\n" - "> + clock-names =3D \"mbx-bus\", \"mbx-3d\", \"mbx\";\n" + "> + clock-names = \"mbx-bus\", \"mbx-3d\", \"mbx\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> sram@30000000 {\n" "> @@ -64,6 +68,8 @@\n" - "> interrupts =3D <6 8>;\n" - "> #address-cells =3D <1>;\n" - "> #size-cells =3D <1>;\n" - "> + clocks =3D <&clks MPC512x_CLK_NFC>;\n" - "> + clock-names =3D \"per\";\n" + "> interrupts = <6 8>;\n" + "> #address-cells = <1>;\n" + "> #size-cells = <1>;\n" + "> + clocks = <&clks MPC512x_CLK_NFC>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> localbus@80000020 {\n" "> @@ -153,12 +159,22 @@\n" - "> compatible =3D \"fsl,mpc5121-mscan\";\n" - "> reg =3D <0x1300 0x80>;\n" - "> interrupts =3D <12 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> compatible = \"fsl,mpc5121-mscan\";\n" + "> reg = <0x1300 0x80>;\n" + "> interrupts = <12 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SYS>,\n" "> + <&clks MPC512x_CLK_REF>,\n" "> + <&clks MPC512x_CLK_MSCAN0_MCLK>;\n" - "> + clock-names =3D \"ips\", \"sys\", \"ref\", \"mclk\";\n" + "> + clock-names = \"ips\", \"sys\", \"ref\", \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> can@1380 {\n" - "> compatible =3D \"fsl,mpc5121-mscan\";\n" - "> reg =3D <0x1380 0x80>;\n" - "> interrupts =3D <13 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> compatible = \"fsl,mpc5121-mscan\";\n" + "> reg = <0x1380 0x80>;\n" + "> interrupts = <13 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SYS>,\n" "> + <&clks MPC512x_CLK_REF>,\n" "> + <&clks MPC512x_CLK_MSCAN1_MCLK>;\n" - "> + clock-names =3D \"ips\", \"sys\", \"ref\", \"mclk\";\n" + "> + clock-names = \"ips\", \"sys\", \"ref\", \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> sdhc@1500 {\n" "> @@ -167,6 +183,9 @@\n" - "> interrupts =3D <8 0x8>;\n" - "> dmas =3D <&dma0 30>;\n" - "> dma-names =3D \"rx-tx\";\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> interrupts = <8 0x8>;\n" + "> dmas = <&dma0 30>;\n" + "> dma-names = \"rx-tx\";\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SDHC>;\n" - "> + clock-names =3D \"ipg\", \"per\";\n" + "> + clock-names = \"ipg\", \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> i2c@1700 {\n" "> @@ -175,6 +194,8 @@\n" - "> compatible =3D \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" - "> reg =3D <0x1700 0x20>;\n" - "> interrupts =3D <9 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_I2C>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" + "> reg = <0x1700 0x20>;\n" + "> interrupts = <9 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_I2C>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> i2c@1720 {\n" "> @@ -183,6 +204,8 @@\n" - "> compatible =3D \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" - "> reg =3D <0x1720 0x20>;\n" - "> interrupts =3D <10 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_I2C>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" + "> reg = <0x1720 0x20>;\n" + "> interrupts = <10 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_I2C>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> i2c@1740 {\n" "> @@ -191,6 +214,8 @@\n" - "> compatible =3D \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" - "> reg =3D <0x1740 0x20>;\n" - "> interrupts =3D <11 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_I2C>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-i2c\", \"fsl-i2c\";\n" + "> reg = <0x1740 0x20>;\n" + "> interrupts = <11 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_I2C>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> i2ccontrol@1760 {\n" "> @@ -202,30 +227,46 @@\n" - "> compatible =3D \"fsl,mpc5121-axe\";\n" - "> reg =3D <0x2000 0x100>;\n" - "> interrupts =3D <42 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_AXE>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-axe\";\n" + "> reg = <0x2000 0x100>;\n" + "> interrupts = <42 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_AXE>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> display@2100 {\n" - "> compatible =3D \"fsl,mpc5121-diu\";\n" - "> reg =3D <0x2100 0x100>;\n" - "> interrupts =3D <64 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_DIU>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-diu\";\n" + "> reg = <0x2100 0x100>;\n" + "> interrupts = <64 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_DIU>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> can@2300 {\n" - "> compatible =3D \"fsl,mpc5121-mscan\";\n" - "> reg =3D <0x2300 0x80>;\n" - "> interrupts =3D <90 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> compatible = \"fsl,mpc5121-mscan\";\n" + "> reg = <0x2300 0x80>;\n" + "> interrupts = <90 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SYS>,\n" "> + <&clks MPC512x_CLK_REF>,\n" "> + <&clks MPC512x_CLK_MSCAN2_MCLK>;\n" - "> + clock-names =3D \"ips\", \"sys\", \"ref\", \"mclk\";\n" + "> + clock-names = \"ips\", \"sys\", \"ref\", \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> can@2380 {\n" - "> compatible =3D \"fsl,mpc5121-mscan\";\n" - "> reg =3D <0x2380 0x80>;\n" - "> interrupts =3D <91 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_IPS>,\n" + "> compatible = \"fsl,mpc5121-mscan\";\n" + "> reg = <0x2380 0x80>;\n" + "> interrupts = <91 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_IPS>,\n" "> + <&clks MPC512x_CLK_SYS>,\n" "> + <&clks MPC512x_CLK_REF>,\n" "> + <&clks MPC512x_CLK_MSCAN3_MCLK>;\n" - "> + clock-names =3D \"ips\", \"sys\", \"ref\", \"mclk\";\n" + "> + clock-names = \"ips\", \"sys\", \"ref\", \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> viu@2400 {\n" - "> compatible =3D \"fsl,mpc5121-viu\";\n" - "> reg =3D <0x2400 0x400>;\n" - "> interrupts =3D <67 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_VIU>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-viu\";\n" + "> reg = <0x2400 0x400>;\n" + "> interrupts = <67 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_VIU>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> mdio@2800 {\n" "> @@ -233,6 +274,8 @@\n" - "> reg =3D <0x2800 0x800>;\n" - "> #address-cells =3D <1>;\n" - "> #size-cells =3D <0>;\n" - "> + clocks =3D <&clks MPC512x_CLK_FEC>;\n" - "> + clock-names =3D \"per\";\n" + "> reg = <0x2800 0x800>;\n" + "> #address-cells = <1>;\n" + "> #size-cells = <0>;\n" + "> + clocks = <&clks MPC512x_CLK_FEC>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> eth0: ethernet@2800 {\n" "> @@ -241,6 +284,8 @@\n" - "> reg =3D <0x2800 0x800>;\n" - "> local-mac-address =3D [ 00 00 00 00 00 00 ];\n" - "> interrupts =3D <4 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_FEC>;\n" - "> + clock-names =3D \"per\";\n" + "> reg = <0x2800 0x800>;\n" + "> local-mac-address = [ 00 00 00 00 00 00 ];\n" + "> interrupts = <4 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_FEC>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* USB1 using external ULPI PHY */\n" "> @@ -252,6 +297,8 @@\n" - "> interrupts =3D <43 0x8>;\n" - "> dr_mode =3D \"otg\";\n" - "> phy_type =3D \"ulpi\";\n" - "> + clocks =3D <&clks MPC512x_CLK_USB1>;\n" - "> + clock-names =3D \"per\";\n" + "> interrupts = <43 0x8>;\n" + "> dr_mode = \"otg\";\n" + "> phy_type = \"ulpi\";\n" + "> + clocks = <&clks MPC512x_CLK_USB1>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* USB0 using internal UTMI PHY */\n" "> @@ -263,6 +310,8 @@\n" - "> interrupts =3D <44 0x8>;\n" - "> dr_mode =3D \"otg\";\n" - "> phy_type =3D \"utmi_wide\";\n" - "> + clocks =3D <&clks MPC512x_CLK_USB2>;\n" - "> + clock-names =3D \"per\";\n" + "> interrupts = <44 0x8>;\n" + "> dr_mode = \"otg\";\n" + "> phy_type = \"utmi_wide\";\n" + "> + clocks = <&clks MPC512x_CLK_USB2>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* IO control */\n" "> @@ -281,6 +330,8 @@\n" - "> compatible =3D \"fsl,mpc5121-pata\";\n" - "> reg =3D <0x10200 0x100>;\n" - "> interrupts =3D <5 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PATA>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-pata\";\n" + "> reg = <0x10200 0x100>;\n" + "> interrupts = <5 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_PATA>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* 512x PSCs are not 52xx PSC compatible */\n" "> @@ -292,6 +343,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC0_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC0_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC1 */\n" "> @@ -301,6 +354,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC1_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC1_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC2 */\n" "> @@ -310,6 +365,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC2_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC2_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC3 */\n" "> @@ -319,6 +376,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC3_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC3_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC4 */\n" "> @@ -328,6 +387,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC4_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC4_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC5 */\n" "> @@ -337,6 +398,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC5_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC5_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC6 */\n" "> @@ -346,6 +409,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC6_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC6_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC7 */\n" "> @@ -355,6 +420,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC7_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC7_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC8 */\n" "> @@ -364,6 +431,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC8_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC8_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC9 */\n" "> @@ -373,6 +442,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC9_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC9_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC10 */\n" "> @@ -382,6 +453,8 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC10_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC10_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> /* PSC11 */\n" "> @@ -391,12 +464,16 @@\n" - "> interrupts =3D <40 0x8>;\n" - "> fsl,rx-fifo-size =3D <16>;\n" - "> fsl,tx-fifo-size =3D <16>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC11_MCLK>;\n" - "> + clock-names =3D \"mclk\";\n" + "> interrupts = <40 0x8>;\n" + "> fsl,rx-fifo-size = <16>;\n" + "> fsl,tx-fifo-size = <16>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC11_MCLK>;\n" + "> + clock-names = \"mclk\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> pscfifo@11f00 {\n" - "> compatible =3D \"fsl,mpc5121-psc-fifo\";\n" - "> reg =3D <0x11f00 0x100>;\n" - "> interrupts =3D <40 0x8>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PSC_FIFO>;\n" - "> + clock-names =3D \"per\";\n" + "> compatible = \"fsl,mpc5121-psc-fifo\";\n" + "> reg = <0x11f00 0x100>;\n" + "> interrupts = <40 0x8>;\n" + "> + clocks = <&clks MPC512x_CLK_PSC_FIFO>;\n" + "> + clock-names = \"per\";\n" "> };\n" - "> =\n" - "\n" + "> \n" "> dma0: dma@14000 {\n" "> @@ -414,6 +491,8 @@\n" - "> #address-cells =3D <3>;\n" - "> #size-cells =3D <2>;\n" - "> #interrupt-cells =3D <1>;\n" - "> + clocks =3D <&clks MPC512x_CLK_PCI>;\n" - "> + clock-names =3D \"per\";\n" - "> =\n" - "\n" - "> reg =3D <0x80008500 0x100 /* internal registers */\n" - "> 0x80008300 0x8>; /* config space access registers =\n" - "*/\n" - "> -- =\n" - "\n" + "> #address-cells = <3>;\n" + "> #size-cells = <2>;\n" + "> #interrupt-cells = <1>;\n" + "> + clocks = <&clks MPC512x_CLK_PCI>;\n" + "> + clock-names = \"per\";\n" + "> \n" + "> reg = <0x80008500 0x100 /* internal registers */\n" + "> 0x80008300 0x8>; /* config space access registers */\n" + "> -- \n" > 1.7.10.4 -d8fa1c964180e3fc3cd43575e95b1b8e6518c4496d531e0175c9270d580e2547 +b21d84ffcd37cae5e2488d248d439ced689b85359e3e5e6f1f0ed044ab04123c
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.