From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 04/13] drm/i915: Kill fbc_enable from hsw_lp_wm_results Date: Wed, 7 Aug 2013 12:57:44 +0300 Message-ID: <20130807095744.GQ5004@intel.com> References: <1375817052-32310-1-git-send-email-ville.syrjala@linux.intel.com> <1375817052-32310-5-git-send-email-ville.syrjala@linux.intel.com> <20130806204511.GN8181@cantiga.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id C9322E5CAB for ; Wed, 7 Aug 2013 02:57:47 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130806204511.GN8181@cantiga.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Aug 06, 2013 at 09:45:11PM +0100, Chris Wilson wrote: > On Tue, Aug 06, 2013 at 10:24:03PM +0300, ville.syrjala@linux.intel.com w= rote: > > From: Ville Syrj=E4l=E4 > > = > > We don't need to store the FBC WM enabled status in each watermark > > level. We anyway have to reduce it down to a single boolean, so just > > delay checking the FBC WM limit until we're computing the final > > value. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > = > The pay-off simply being the reduction of one bool in a temporary > struct [x3]? I don't remember anymore if I had a better reason originally. > = > Reviewed-by: Chris Wilson > -Chris > = > -- = > Chris Wilson, Intel Open Source Technology Centre -- = Ville Syrj=E4l=E4 Intel OTC