From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/9] drm/i915: Update rules for writing through the LLC with the cpu
Date: Thu, 8 Aug 2013 18:51:26 +0300 [thread overview]
Message-ID: <20130808155126.GA5004@intel.com> (raw)
In-Reply-To: <20130808153635.GB30355@cantiga.alporthouse.com>
On Thu, Aug 08, 2013 at 04:36:35PM +0100, Chris Wilson wrote:
> On Thu, Aug 08, 2013 at 06:27:12PM +0300, Ville Syrjälä wrote:
> > On Thu, Aug 08, 2013 at 02:41:05PM +0100, Chris Wilson wrote:
> > > if (!needs_clflush_after &&
> > > obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
> > > - i915_gem_clflush_object(obj);
> > > + i915_gem_clflush_object(obj, false);
> >
> > Shouldn't that be i915_gem_clflush_object(obj, obj->pin_display) ?
>
> !needs_clflush_after implies that we cache-coherent and not writing to a
> scanout, so obj->pin_display must be false here.
But we dropped the lock in the slow path, so couldn't it have changed?
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2013-08-08 15:51 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-08 13:41 [PATCH 1/9] drm/i915: Update rules for reading cache lines through the LLC Chris Wilson
2013-08-08 13:41 ` [PATCH 2/9] drm/i915: Track when an object is pinned for use by the display engine Chris Wilson
2013-08-09 11:25 ` [PATCH] " Chris Wilson
2013-08-09 11:54 ` Ville Syrjälä
2013-08-08 13:41 ` [PATCH 3/9] drm/i915: Update rules for writing through the LLC with the cpu Chris Wilson
2013-08-08 15:27 ` Ville Syrjälä
2013-08-08 15:36 ` Chris Wilson
2013-08-08 15:51 ` Ville Syrjälä [this message]
2013-08-08 16:12 ` Chris Wilson
2013-08-09 11:26 ` [PATCH] " Chris Wilson
2013-08-09 11:56 ` Ville Syrjälä
2013-08-08 13:41 ` [PATCH 4/9] drm/i915: Allow the GPU to cache stolen memory Chris Wilson
2013-08-08 13:41 ` [PATCH 5/9] drm/i915: Allocate LLC ringbuffers from stolen Chris Wilson
2013-08-08 13:41 ` [PATCH 6/9] drm/i915: Allocate context objects " Chris Wilson
2013-08-10 9:25 ` Daniel Vetter
2013-08-10 9:34 ` Chris Wilson
2013-08-10 9:44 ` Daniel Vetter
2013-08-08 13:41 ` [PATCH 7/9] drm/i915: Only do a chipset flush after a clflush Chris Wilson
2013-08-08 13:41 ` [PATCH 8/9] drm/i915: Use Write-Through cacheing for the display plane on Iris Chris Wilson
2013-08-08 13:41 ` [PATCH 9/9] drm/i915: Allow the user to set bo into the DISPLAY cache domain Chris Wilson
2013-08-10 10:09 ` Daniel Vetter
2013-08-10 10:19 ` Chris Wilson
2013-08-10 12:54 ` [PATCH] drm/i915: reserve I915_CACHING_DISPLAY and document cache modes Daniel Vetter
2013-08-10 12:57 ` Daniel Vetter
2013-08-10 13:09 ` Chris Wilson
2013-08-10 15:54 ` Daniel Vetter
2013-08-12 16:53 ` [PATCH 9/9] drm/i915: Allow the user to set bo into the DISPLAY cache domain Daniel Vetter
2013-08-08 16:42 ` [PATCH 1/9] drm/i915: Update rules for reading cache lines through the LLC Ville Syrjälä
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