From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Align tiled scanouts from stolen memory to 256k in the GTT Date: Mon, 12 Aug 2013 12:38:03 +0300 Message-ID: <20130812093803.GC7159@intel.com> References: <1376259448-7856-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id BDCB5E5F03 for ; Mon, 12 Aug 2013 02:38:06 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1376259448-7856-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sun, Aug 11, 2013 at 11:17:28PM +0100, Chris Wilson wrote: > For unfathomable reasons this alignment appears to be required for tiled > scanouts being read from stolen memory. I can find no reference in the > w/a db to support this requirement, but the evidence of my own eyes says > this prevents many headaches. > = > Note that I have not tricked anything older than Sandybridge into using > stolen tiled scanouts, so the extra alignment may be required there as > well. Strange. I can't find anything except async flips and vt-d which would require 256k alignment. > = > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/intel_display.c | 2 ++ > 1 file changed, 2 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 6b7ce06..a7573f2 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1848,6 +1848,8 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, > case I915_TILING_X: > /* pin() will align the object as required by fence */ > alignment =3D 0; > + if (obj->stolen && INTEL_INFO(dev)->gen >=3D 6) > + alignment =3D 256 * 1024; > break; > case I915_TILING_Y: > /* Despite that we check this in framebuffer_init userspace can > -- = > 1.8.4.rc2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC