* [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode
@ 2013-08-15 4:59 vandana.kannan
2013-08-15 4:59 ` [PATCH 2/3] [VPG HSW-A] drm/i915: Add PAR support in AVI infoframe vandana.kannan
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: vandana.kannan @ 2013-08-15 4:59 UTC (permalink / raw)
To: dri-devel; +Cc: vkannan
From: vkannan <vandana.kannan@intel.com>
Mode is the video format, which is the information the sink needs to
properly display an image. a complete definition of video format includes
video timing, picture aspect ratio, color space, quantization range,
component depth.
video format timing may be associated with more than 1 video format
for example, 720x480p formatted in the 4:3 Picture Aspect Ratio or a
720x480p formatted in the 16:9 Picture Aspect Ratio.
For HDMI compliance, a set of CEA modes are tested (CEA 861-D table 3).
This list has 64 modes. When one of the modes are set, the corresponding
fields should show up correctly (as mentioned in Table 3 of CEA spec).
For picture aspect ratio, if the mode is found from the CEA mode list,
the corresponding PAR is sent as part of infoframe. If the mode to be set
is not part of the CEA mode list, PAR is calculated from resolution.
CEA modes have a specific picture aspect ratio. Adding this field
as part of drm_display_mode. This is required to be sent as part of AVI
infoframe for HDMI compliance.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/drm_edid.c | 374 ++++++++++++++++++-------------
drivers/gpu/drm/gma500/oaktrail_lvds.c | 14 +-
drivers/gpu/drm/gma500/psb_intel_sdvo.c | 38 ++--
drivers/gpu/drm/i915/intel_display.c | 3 +-
drivers/gpu/drm/i915/intel_sdvo.c | 38 ++--
include/drm/drm_crtc.h | 7 +-
6 files changed, 265 insertions(+), 209 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e8d17ee..83e2fda 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -135,378 +135,379 @@ static const struct drm_display_mode drm_dmt_modes[] = {
/* 640x350@85Hz */
{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
736, 832, 0, 350, 382, 385, 445, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 640x400@85Hz */
{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
736, 832, 0, 400, 401, 404, 445, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 720x400@85Hz */
{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
828, 936, 0, 400, 401, 404, 446, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 640x480@60Hz */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752, 800, 0, 480, 489, 492, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 640x480@72Hz */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
704, 832, 0, 480, 489, 492, 520, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 640x480@75Hz */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
720, 840, 0, 480, 481, 484, 500, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 640x480@85Hz */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
752, 832, 0, 480, 481, 484, 509, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 800x600@56Hz */
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
896, 1024, 0, 600, 601, 603, 625, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 800x600@60Hz */
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
968, 1056, 0, 600, 601, 605, 628, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 800x600@72Hz */
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
976, 1040, 0, 600, 637, 643, 666, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 800x600@75Hz */
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
896, 1056, 0, 600, 601, 604, 625, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 800x600@85Hz */
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
896, 1048, 0, 600, 601, 604, 631, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 800x600@120Hz RB */
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
880, 960, 0, 600, 603, 607, 636, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 848x480@60Hz */
{ DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
976, 1088, 0, 480, 486, 494, 517, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1024x768@43Hz, interlace */
{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
1208, 1264, 0, 768, 768, 772, 817, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
- DRM_MODE_FLAG_INTERLACE) },
+ DRM_MODE_FLAG_INTERLACE, 0) },
/* 1024x768@60Hz */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1184, 1344, 0, 768, 771, 777, 806, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1024x768@70Hz */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
1184, 1328, 0, 768, 771, 777, 806, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1024x768@75Hz */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
1136, 1312, 0, 768, 769, 772, 800, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1024x768@85Hz */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
1168, 1376, 0, 768, 769, 772, 808, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1024x768@120Hz RB */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
1104, 1184, 0, 768, 771, 775, 813, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1152x864@75Hz */
{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1344, 1600, 0, 864, 865, 868, 900, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x768@60Hz RB */
{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
1360, 1440, 0, 768, 771, 778, 790, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1280x768@60Hz */
{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
1472, 1664, 0, 768, 771, 778, 798, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x768@75Hz */
{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
1488, 1696, 0, 768, 771, 778, 805, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1280x768@85Hz */
{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
1496, 1712, 0, 768, 771, 778, 809, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x768@120Hz RB */
{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
1360, 1440, 0, 768, 771, 778, 813, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1280x800@60Hz RB */
{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
1360, 1440, 0, 800, 803, 809, 823, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1280x800@60Hz */
{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
1480, 1680, 0, 800, 803, 809, 831, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1280x800@75Hz */
{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
1488, 1696, 0, 800, 803, 809, 838, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x800@85Hz */
{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
1496, 1712, 0, 800, 803, 809, 843, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x800@120Hz RB */
{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
1360, 1440, 0, 800, 803, 809, 847, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1280x960@60Hz */
{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
1488, 1800, 0, 960, 961, 964, 1000, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x960@85Hz */
{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
1504, 1728, 0, 960, 961, 964, 1011, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x960@120Hz RB */
{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
1360, 1440, 0, 960, 963, 967, 1017, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1280x1024@60Hz */
{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x1024@75Hz */
{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x1024@85Hz */
{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1280x1024@120Hz RB */
{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1360x768@60Hz */
{ DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
1536, 1792, 0, 768, 771, 777, 795, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1360x768@120Hz RB */
{ DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
1440, 1520, 0, 768, 771, 776, 813, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1400x1050@60Hz RB */
{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1400x1050@60Hz */
{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1400x1050@75Hz */
{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1400x1050@85Hz */
{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1400x1050@120Hz RB */
{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1440x900@60Hz RB */
{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
1520, 1600, 0, 900, 903, 909, 926, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1440x900@60Hz */
{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
1672, 1904, 0, 900, 903, 909, 934, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1440x900@75Hz */
{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
1688, 1936, 0, 900, 903, 909, 942, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1440x900@85Hz */
{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
1696, 1952, 0, 900, 903, 909, 948, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1440x900@120Hz RB */
{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
1520, 1600, 0, 900, 903, 909, 953, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1600x1200@60Hz */
{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1600x1200@65Hz */
{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1600x1200@70Hz */
{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1600x1200@75Hz */
{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1600x1200@85Hz */
{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1600x1200@120Hz RB */
{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1680x1050@60Hz RB */
{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1680x1050@60Hz */
{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1680x1050@75Hz */
{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1680x1050@85Hz */
{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1680x1050@120Hz RB */
{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1792x1344@60Hz */
{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1792x1344@75Hz */
{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1792x1344@120Hz RB */
{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1856x1392@60Hz */
{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1856x1392@75Hz */
{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1856x1392@120Hz RB */
{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1920x1200@60Hz RB */
{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1920x1200@60Hz */
{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1920x1200@75Hz */
{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1920x1200@85Hz */
{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1920x1200@120Hz RB */
{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 1920x1440@60Hz */
{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1920x1440@75Hz */
{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 1920x1440@120Hz RB */
{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 2560x1600@60Hz RB */
{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
/* 2560x1600@60Hz */
{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 2560x1600@75HZ */
{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 2560x1600@85HZ */
{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
/* 2560x1600@120Hz RB */
{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
};
static const struct drm_display_mode edid_est_modes[] = {
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
968, 1056, 0, 600, 601, 605, 628, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) }, /* 800x600@60Hz */
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
896, 1024, 0, 600, 601, 603, 625, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) }, /* 800x600@56Hz */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
720, 840, 0, 480, 481, 484, 500, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) }, /* 640x480@75Hz */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
704, 832, 0, 480, 489, 491, 520, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) }, /* 640x480@72Hz */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
768, 864, 0, 480, 483, 486, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) }, /* 640x480@67Hz */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
752, 800, 0, 480, 490, 492, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) }, /* 640x480@60Hz */
{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
846, 900, 0, 400, 421, 423, 449, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) }, /* 720x400@88Hz */
{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
846, 900, 0, 400, 412, 414, 449, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC, 0) }, /* 720x400@70Hz */
{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) }, /* 1280x1024@75Hz */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
1136, 1312, 0, 768, 769, 772, 800, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) }, /* 1024x768@75Hz */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
1184, 1328, 0, 768, 771, 777, 806, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) }, /* 1024x768@70Hz */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1184, 1344, 0, 768, 771, 777, 806, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) }, /* 1024x768@60Hz */
{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
1208, 1264, 0, 768, 768, 776, 817, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
+ DRM_MODE_FLAG_INTERLACE, 0) }, /* 1024x768@43Hz */
{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
928, 1152, 0, 624, 625, 628, 667, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0) }, /* 832x624@75Hz */
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
896, 1056, 0, 600, 601, 604, 625, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) }, /* 800x600@75Hz */
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
976, 1040, 0, 600, 637, 643, 666, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) }, /* 800x600@72Hz */
{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1344, 1600, 0, 864, 865, 868, 900, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) }, /* 1152x864@75Hz */
};
struct minimode {
@@ -585,349 +586,398 @@ static const struct minimode extra_modes[] = {
*/
static const struct drm_display_mode edid_cea_modes[] = {
/* 1 - 640x480@60Hz */
- { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
+ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
752, 800, 0, 480, 490, 492, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 60, },
/* 2 - 720x480@60Hz */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 60, },
/* 3 - 720x480@60Hz */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 4 - 1280x720@60Hz */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1430, 1650, 0, 720, 725, 730, 750, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 5 - 1920x1080i@60Hz */
{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
- DRM_MODE_FLAG_INTERLACE),
+ DRM_MODE_FLAG_INTERLACE, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 6 - 1440x480i@60Hz */
{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 60, },
/* 7 - 1440x480i@60Hz */
{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 8 - 1440x240@60Hz */
{ DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 240, 244, 247, 262, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_DBLCLK, HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 60, },
/* 9 - 1440x240@60Hz */
{ DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
1602, 1716, 0, 240, 244, 247, 262, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_DBLCLK, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 10 - 2880x480i@60Hz */
{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE),
+ DRM_MODE_FLAG_INTERLACE, HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 60, },
/* 11 - 2880x480i@60Hz */
{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE),
+ DRM_MODE_FLAG_INTERLACE, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 12 - 2880x240@60Hz */
{ DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 240, 244, 247, 262, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 60, },
/* 13 - 2880x240@60Hz */
{ DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
3204, 3432, 0, 240, 244, 247, 262, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 14 - 1440x480@60Hz */
{ DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
1596, 1716, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 60, },
/* 15 - 1440x480@60Hz */
{ DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
1596, 1716, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 16 - 1920x1080@60Hz */
{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 17 - 720x576@50Hz */
{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
796, 864, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 50, },
/* 18 - 720x576@50Hz */
{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
796, 864, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 19 - 1280x720@50Hz */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1760, 1980, 0, 720, 725, 730, 750, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 20 - 1920x1080i@50Hz */
{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
- DRM_MODE_FLAG_INTERLACE),
+ DRM_MODE_FLAG_INTERLACE, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 21 - 1440x576i@50Hz */
{ DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
1590, 1728, 0, 576, 580, 586, 625, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 50, },
/* 22 - 1440x576i@50Hz */
{ DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
1590, 1728, 0, 576, 580, 586, 625, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 23 - 1440x288@50Hz */
{ DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
1590, 1728, 0, 288, 290, 293, 312, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_DBLCLK, HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 50, },
/* 24 - 1440x288@50Hz */
{ DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
1590, 1728, 0, 288, 290, 293, 312, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_DBLCLK, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 25 - 2880x576i@50Hz */
{ DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
3180, 3456, 0, 576, 580, 586, 625, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE),
+ DRM_MODE_FLAG_INTERLACE, HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 50, },
/* 26 - 2880x576i@50Hz */
{ DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
3180, 3456, 0, 576, 580, 586, 625, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE),
+ DRM_MODE_FLAG_INTERLACE, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 27 - 2880x288@50Hz */
{ DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
3180, 3456, 0, 288, 290, 293, 312, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 50, },
/* 28 - 2880x288@50Hz */
{ DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
3180, 3456, 0, 288, 290, 293, 312, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 29 - 1440x576@50Hz */
{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
1592, 1728, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 50, },
/* 30 - 1440x576@50Hz */
{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
1592, 1728, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 31 - 1920x1080@50Hz */
{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 32 - 1920x1080@24Hz */
{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 24, },
/* 33 - 1920x1080@25Hz */
{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 25, },
/* 34 - 1920x1080@30Hz */
{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 30, },
/* 35 - 2880x480@60Hz */
{ DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
3192, 3432, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 60, },
/* 36 - 2880x480@60Hz */
{ DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
3192, 3432, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 60, },
/* 37 - 2880x576@50Hz */
{ DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
3184, 3456, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 50, },
/* 38 - 2880x576@50Hz */
{ DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
3184, 3456, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 39 - 1920x1080i@50Hz */
{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE),
+ DRM_MODE_FLAG_INTERLACE, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 50, },
/* 40 - 1920x1080i@100Hz */
{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
- DRM_MODE_FLAG_INTERLACE),
+ DRM_MODE_FLAG_INTERLACE, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 100, },
/* 41 - 1280x720@100Hz */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1760, 1980, 0, 720, 725, 730, 750, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 100, },
/* 42 - 720x576@100Hz */
{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
796, 864, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 100, },
/* 43 - 720x576@100Hz */
{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
796, 864, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 100, },
/* 44 - 1440x576i@100Hz */
{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
1590, 1728, 0, 576, 580, 586, 625, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_DBLCLK, HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 100, },
/* 45 - 1440x576i@100Hz */
{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
1590, 1728, 0, 576, 580, 586, 625, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_DBLCLK, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 100, },
/* 46 - 1920x1080i@120Hz */
{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
- DRM_MODE_FLAG_INTERLACE),
+ DRM_MODE_FLAG_INTERLACE, HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 120, },
/* 47 - 1280x720@120Hz */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1430, 1650, 0, 720, 725, 730, 750, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 120, },
/* 48 - 720x480@120Hz */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 120, },
/* 49 - 720x480@120Hz */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 120, },
/* 50 - 1440x480i@120Hz */
{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 120, },
/* 51 - 1440x480i@120Hz */
{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 120, },
/* 52 - 720x576@200Hz */
{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
796, 864, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 200, },
/* 53 - 720x576@200Hz */
{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
796, 864, 0, 576, 581, 586, 625, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 200, },
/* 54 - 1440x576i@200Hz */
{ DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
1590, 1728, 0, 576, 580, 586, 625, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 200, },
/* 55 - 1440x576i@200Hz */
{ DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
1590, 1728, 0, 576, 580, 586, 625, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 200, },
/* 56 - 720x480@240Hz */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 240, },
/* 57 - 720x480@240Hz */
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 240, },
/* 58 - 1440x480i@240 */
{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_4_3),
.vrefresh = 240, },
/* 59 - 1440x480i@240 */
{ DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
1602, 1716, 0, 480, 488, 494, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 240, },
/* 60 - 1280x720@24Hz */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
3080, 3300, 0, 720, 725, 730, 750, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 24, },
/* 61 - 1280x720@25Hz */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
3740, 3960, 0, 720, 725, 730, 750, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 25, },
/* 62 - 1280x720@30Hz */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
3080, 3300, 0, 720, 725, 730, 750, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 30, },
/* 63 - 1920x1080@120Hz */
{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 120, },
/* 64 - 1920x1080@100Hz */
{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+ HDMI_PICTURE_ASPECT_16_9),
.vrefresh = 100, },
};
diff --git a/drivers/gpu/drm/gma500/oaktrail_lvds.c b/drivers/gpu/drm/gma500/oaktrail_lvds.c
index 325013a..eb9977b 100644
--- a/drivers/gpu/drm/gma500/oaktrail_lvds.c
+++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c
@@ -224,25 +224,25 @@ static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
static struct drm_display_mode lvds_configuration_modes[] = {
/* hard coded fixed mode for TPO LTPS LPJ040K001A */
{ DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 33264, 800, 836,
- 846, 1056, 0, 480, 489, 491, 525, 0, 0) },
+ 846, 1056, 0, 480, 489, 491, 525, 0, 0, 0) },
/* hard coded fixed mode for LVDS 800x480 */
{ DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30994, 800, 801,
- 802, 1024, 0, 480, 481, 482, 525, 0, 0) },
+ 802, 1024, 0, 480, 481, 482, 525, 0, 0, 0) },
/* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
{ DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1072,
- 1104, 1184, 0, 600, 603, 604, 608, 0, 0) },
+ 1104, 1184, 0, 600, 603, 604, 608, 0, 0, 0) },
/* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
{ DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1104,
- 1136, 1184, 0, 600, 603, 604, 608, 0, 0) },
+ 1136, 1184, 0, 600, 603, 604, 608, 0, 0, 0) },
/* hard coded fixed mode for Sharp wsvga LVDS 1024x600 */
{ DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 48885, 1024, 1124,
- 1204, 1312, 0, 600, 607, 610, 621, 0, 0) },
+ 1204, 1312, 0, 600, 607, 610, 621, 0, 0, 0) },
/* hard coded fixed mode for LVDS 1024x768 */
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
- 1184, 1344, 0, 768, 771, 777, 806, 0, 0) },
+ 1184, 1344, 0, 768, 771, 777, 806, 0, 0, 0) },
/* hard coded fixed mode for LVDS 1366x768 */
{ DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 77500, 1366, 1430,
- 1558, 1664, 0, 768, 769, 770, 776, 0, 0) },
+ 1558, 1664, 0, 768, 769, 770, 776, 0, 0, 0) },
};
/* Returns the panel fixed mode from configuration. */
diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
index 19e3660..b9d0a35 100644
--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
@@ -1464,61 +1464,61 @@ static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector)
static const struct drm_display_mode sdvo_tv_modes[] = {
{ DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
416, 0, 200, 201, 232, 233, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
416, 0, 240, 241, 272, 273, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
496, 0, 300, 301, 332, 333, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
736, 0, 350, 351, 382, 383, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
736, 0, 400, 401, 432, 433, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
736, 0, 480, 481, 512, 513, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
800, 0, 480, 481, 512, 513, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
800, 0, 576, 577, 608, 609, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
816, 0, 350, 351, 382, 383, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
816, 0, 400, 401, 432, 433, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
816, 0, 480, 481, 512, 513, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
816, 0, 540, 541, 572, 573, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
816, 0, 576, 577, 608, 609, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
864, 0, 576, 577, 608, 609, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
896, 0, 600, 601, 632, 633, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
928, 0, 624, 625, 656, 657, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1016, 0, 766, 767, 798, 799, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1120, 0, 768, 769, 800, 801, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1376, 0, 1024, 1025, 1056, 1057, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
};
static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 24e0681..ce5a076 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6646,7 +6646,8 @@ static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
/* VESA 640x480x72Hz mode to set on the pipe */
static struct drm_display_mode load_detect_mode = {
DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
- 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+ 704, 832, 0, 480, 489, 491, 520, 0,
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 0),
};
static struct drm_framebuffer *
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 6a8c90e..5f9dc05 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1787,61 +1787,61 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
static const struct drm_display_mode sdvo_tv_modes[] = {
{ DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
416, 0, 200, 201, 232, 233, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
416, 0, 240, 241, 272, 273, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
496, 0, 300, 301, 332, 333, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
736, 0, 350, 351, 382, 383, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
736, 0, 400, 401, 432, 433, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
736, 0, 480, 481, 512, 513, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
800, 0, 480, 481, 512, 513, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
800, 0, 576, 577, 608, 609, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
816, 0, 350, 351, 382, 383, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
816, 0, 400, 401, 432, 433, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
816, 0, 480, 481, 512, 513, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
816, 0, 540, 541, 572, 573, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
816, 0, 576, 577, 608, 609, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
864, 0, 576, 577, 608, 609, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
896, 0, 600, 601, 632, 633, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
928, 0, 624, 625, 656, 657, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1016, 0, 766, 767, 798, 799, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1120, 0, 768, 769, 800, 801, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1376, 0, 1024, 1025, 1056, 1057, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 0) },
};
static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 9779ea1..07c0d58 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -30,6 +30,7 @@
#include <linux/types.h>
#include <linux/idr.h>
#include <linux/fb.h>
+#include <linux/hdmi.h>
#include <drm/drm_mode.h>
#include <drm/drm_fourcc.h>
@@ -115,12 +116,14 @@ enum drm_mode_status {
#define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \
DRM_MODE_TYPE_CRTC_C)
-#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \
+#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f, \
+ ar) \
.name = nm, .status = 0, .type = (t), .clock = (c), \
.hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
.htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
.vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
.vscan = (vs), .flags = (f), \
+ .picture_aspect_ratio = (ar), \
.base.type = DRM_MODE_OBJECT_MODE
#define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */
@@ -177,6 +180,8 @@ struct drm_display_mode {
int vrefresh; /* in Hz */
int hsync; /* in kHz */
+
+ enum hdmi_picture_aspect picture_aspect_ratio;
};
enum drm_connector_status {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/3] [VPG HSW-A] drm/i915: Add PAR support in AVI infoframe
2013-08-15 4:59 [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode vandana.kannan
@ 2013-08-15 4:59 ` vandana.kannan
2013-08-15 7:32 ` Ville Syrjälä
2013-08-15 4:59 ` [PATCH 3/3] [VPG HSW-A] drm/i915: Populate all fields of " vandana.kannan
2013-08-15 7:06 ` [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode Ville Syrjälä
2 siblings, 1 reply; 10+ messages in thread
From: vandana.kannan @ 2013-08-15 4:59 UTC (permalink / raw)
To: dri-devel; +Cc: vkannan
From: vkannan <vandana.kannan@intel.com>
Populate picture aspect ratio field of AVI infoframe.
If there is a custom value to be set for aspect ratio, it takes highest
priority, followed by a check in the CEA mode list. If the mode is not
found in the standard mode list, aspect ratio is calculated based on aspect
ratio.
Priority of PAR value: 1. custom value, 2. based on CEA mode list,
3. calculate from resolution
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/drm_edid.c | 7 +++++++
drivers/gpu/drm/i915/intel_hdmi.c | 25 +++++++++++++++++++++++++
include/drm/drm_crtc.h | 1 +
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 83e2fda..110a56f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2427,6 +2427,13 @@ u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
}
EXPORT_SYMBOL(drm_match_cea_mode);
+enum hdmi_picture_aspect drm_get_cea_aspect_ratio(u8 vic)
+{
+ /*return Aspect Ratio for VIC-1 to access the right array element*/
+ return edid_cea_modes[vic-1].picture_aspect_ratio;
+}
+EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
+
static int
add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
{
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 1e6b5cf..7cf6fc5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -29,6 +29,7 @@
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
+#include <linux/hdmi.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
@@ -334,10 +335,12 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
{
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+ enum hdmi_picture_aspect PAR;
struct dip_infoframe avi_if = {
.type = DIP_TYPE_AVI,
.ver = DIP_VERSION_AVI,
.len = DIP_LEN_AVI,
+ .body.avi.C_M_R = 8,
};
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
@@ -352,6 +355,28 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
+ /*If picture aspect ratio (PAR) is set to custom value, then use that,
+ else if VIC > 1, then get PAR from CEA mode list, else, calculate
+ PAR based on resolution */
+ if (adjusted_mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
+ adjusted_mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) {
+ avi_if.body.avi.C_M_R |=
+ adjusted_mode->picture_aspect_ratio << 4;
+ /*PAR is bit 5:4 of data byte 2 of AVI infoframe */
+ } else if (avi_if.body.avi.VIC) {
+ PAR = drm_get_cea_aspect_ratio(avi_if.body.avi.VIC);
+ avi_if.body.avi.C_M_R |= PAR << 4;
+ } else {
+ if (!(adjusted_mode->vdisplay % 3) &&
+ ((adjusted_mode->vdisplay * 4 / 3) ==
+ adjusted_mode->hdisplay))
+ avi_if.body.avi.C_M_R |= HDMI_PICTURE_ASPECT_4_3 << 4;
+ else if (!(adjusted_mode->vdisplay % 9) &&
+ ((adjusted_mode->vdisplay * 16 / 9) ==
+ adjusted_mode->hdisplay))
+ avi_if.body.avi.C_M_R |= HDMI_PICTURE_ASPECT_16_9 << 4;
+ }
+
intel_set_infoframe(encoder, &avi_if);
}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 07c0d58..e215bcc 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1048,6 +1048,7 @@ extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
extern u8 *drm_find_cea_extension(struct edid *edid);
extern u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
+extern enum hdmi_picture_aspect drm_get_cea_aspect_ratio(u8 vic);
extern bool drm_detect_hdmi_monitor(struct edid *edid);
extern bool drm_detect_monitor_audio(struct edid *edid);
extern bool drm_rgb_quant_range_selectable(struct edid *edid);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/3] [VPG HSW-A] drm/i915: Add PAR support in AVI infoframe
2013-08-15 4:59 ` [PATCH 2/3] [VPG HSW-A] drm/i915: Add PAR support in AVI infoframe vandana.kannan
@ 2013-08-15 7:32 ` Ville Syrjälä
0 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjälä @ 2013-08-15 7:32 UTC (permalink / raw)
To: vandana.kannan; +Cc: dri-devel
On Thu, Aug 15, 2013 at 10:29:02AM +0530, vandana.kannan@intel.com wrote:
> From: vkannan <vandana.kannan@intel.com>
>
> Populate picture aspect ratio field of AVI infoframe.
> If there is a custom value to be set for aspect ratio, it takes highest
> priority, followed by a check in the CEA mode list. If the mode is not
> found in the standard mode list, aspect ratio is calculated based on aspect
> ratio.
>
> Priority of PAR value: 1. custom value, 2. based on CEA mode list,
> 3. calculate from resolution
There's been a lot of change to the infoframe code lately. We're
using the generic infoframe helpers these days, so this thing will need
to be rebased.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/drm_edid.c | 7 +++++++
> drivers/gpu/drm/i915/intel_hdmi.c | 25 +++++++++++++++++++++++++
> include/drm/drm_crtc.h | 1 +
> 3 files changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 83e2fda..110a56f 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2427,6 +2427,13 @@ u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
> }
> EXPORT_SYMBOL(drm_match_cea_mode);
>
> +enum hdmi_picture_aspect drm_get_cea_aspect_ratio(u8 vic)
> +{
> + /*return Aspect Ratio for VIC-1 to access the right array element*/
> + return edid_cea_modes[vic-1].picture_aspect_ratio;
> +}
> +EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
> +
> static int
> add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
> {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 1e6b5cf..7cf6fc5 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -29,6 +29,7 @@
> #include <linux/i2c.h>
> #include <linux/slab.h>
> #include <linux/delay.h>
> +#include <linux/hdmi.h>
> #include <drm/drmP.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_edid.h>
> @@ -334,10 +335,12 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
> {
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
> + enum hdmi_picture_aspect PAR;
> struct dip_infoframe avi_if = {
> .type = DIP_TYPE_AVI,
> .ver = DIP_VERSION_AVI,
> .len = DIP_LEN_AVI,
> + .body.avi.C_M_R = 8,
> };
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> @@ -352,6 +355,28 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
>
> avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
>
> + /*If picture aspect ratio (PAR) is set to custom value, then use that,
> + else if VIC > 1, then get PAR from CEA mode list, else, calculate
> + PAR based on resolution */
> + if (adjusted_mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
> + adjusted_mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) {
> + avi_if.body.avi.C_M_R |=
> + adjusted_mode->picture_aspect_ratio << 4;
> + /*PAR is bit 5:4 of data byte 2 of AVI infoframe */
> + } else if (avi_if.body.avi.VIC) {
> + PAR = drm_get_cea_aspect_ratio(avi_if.body.avi.VIC);
> + avi_if.body.avi.C_M_R |= PAR << 4;
> + } else {
> + if (!(adjusted_mode->vdisplay % 3) &&
> + ((adjusted_mode->vdisplay * 4 / 3) ==
> + adjusted_mode->hdisplay))
> + avi_if.body.avi.C_M_R |= HDMI_PICTURE_ASPECT_4_3 << 4;
> + else if (!(adjusted_mode->vdisplay % 9) &&
> + ((adjusted_mode->vdisplay * 16 / 9) ==
> + adjusted_mode->hdisplay))
> + avi_if.body.avi.C_M_R |= HDMI_PICTURE_ASPECT_16_9 << 4;
> + }
I think what we need is a new property to control the aspect ratio.
I'm thinking something like this:
enum {
"Automatic",
"Preferred", /* M=0 /*
"4:3", /* M=1 */
"16:9", /* M=2 */
}
If the user selects anything but "Automatic" we just directly set the M
bits to the appropriate value. Also we should probably extend
drm_match_cea_mode() so that it will also compare the user provided
aspect ratio w/ the VIC aspect ratio. That way we would send a VIC which
matches (in the 4:3 and 16:9 cases) the user selected aspect ratio.
Although the spec does say that the M bits will take precendence over
the VIC, but given how badly this stuff is generally implemented in
displays, I have a feeling that some displays might only look at the VIC.
For the "Automatic" case we should just pick the first VIC that
otherwise matches the display mode. If there's no VIC for the mode, we
could just send M=0, or we could try to determine the aspect ratio from
the resolution like in your patch.
> +
> intel_set_infoframe(encoder, &avi_if);
> }
>
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 07c0d58..e215bcc 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -1048,6 +1048,7 @@ extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
> void *data, struct drm_file *file_priv);
> extern u8 *drm_find_cea_extension(struct edid *edid);
> extern u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
> +extern enum hdmi_picture_aspect drm_get_cea_aspect_ratio(u8 vic);
> extern bool drm_detect_hdmi_monitor(struct edid *edid);
> extern bool drm_detect_monitor_audio(struct edid *edid);
> extern bool drm_rgb_quant_range_selectable(struct edid *edid);
> --
> 1.7.9.5
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] [VPG HSW-A] drm/i915: Populate all fields of AVI infoframe
2013-08-15 4:59 [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode vandana.kannan
2013-08-15 4:59 ` [PATCH 2/3] [VPG HSW-A] drm/i915: Add PAR support in AVI infoframe vandana.kannan
@ 2013-08-15 4:59 ` vandana.kannan
2013-08-15 7:43 ` Ville Syrjälä
2013-08-15 7:06 ` [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode Ville Syrjälä
2 siblings, 1 reply; 10+ messages in thread
From: vandana.kannan @ 2013-08-15 4:59 UTC (permalink / raw)
To: dri-devel; +Cc: vkannan
From: vkannan <vandana.kannan@intel.com>
Populate bar information, colorimetry, IT content, quantization range fields
of AVI infoframe based on CEA 861-D spec.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 4 ++++
drivers/gpu/drm/i915/intel_hdmi.c | 39 +++++++++++++++++++++++++++++++++++--
2 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 97df85d..e02c442 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -412,6 +412,10 @@ struct cxsr_latency {
#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
+#define DIP_AVI_IT_CONTENT (1 << 7)
+#define DIP_AVI_BAR_BOTH (3 << 2)
+#define DIP_AVI_COLOR_ITU601 (1 << 6)
+#define DIP_AVI_COLOR_ITU709 (2 << 6)
#define DIP_TYPE_SPD 0x83
#define DIP_VERSION_SPD 0x1
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 7cf6fc5..dbbc02b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -340,9 +340,22 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
.type = DIP_TYPE_AVI,
.ver = DIP_VERSION_AVI,
.len = DIP_LEN_AVI,
+ .body.avi.Y_A_B_S = 0,
.body.avi.C_M_R = 8,
+ .body.avi.ITC_EC_Q_SC = 0,
+ .body.avi.VIC = 0,
+ .body.avi.YQ_CN_PR = 0,
+ .body.avi.top_bar_end = 0,
+ .body.avi.bottom_bar_start = 0,
+ .body.avi.left_bar_end = 0,
+ .body.avi.right_bar_start = 0,
};
+ /* Bar information */
+ avi_if.body.avi.Y_A_B_S |= DIP_AVI_BAR_BOTH;
+
+ avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
+
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
@@ -351,10 +364,17 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
else
avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
+ } else {
+ /* Set full range quantization for non-CEA modes
+ and 640x480 */
+ if ((avi_if.body.avi.VIC == 0) || (avi_if.body.avi.VIC == 1))
+ avi_if.body.avi.ITC_EC_Q_SC |=
+ DIP_AVI_RGB_QUANT_RANGE_FULL;
+ else
+ avi_if.body.avi.ITC_EC_Q_SC |=
+ DIP_AVI_RGB_QUANT_RANGE_LIMITED;
}
- avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
-
/*If picture aspect ratio (PAR) is set to custom value, then use that,
else if VIC > 1, then get PAR from CEA mode list, else, calculate
PAR based on resolution */
@@ -377,6 +397,21 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
avi_if.body.avi.C_M_R |= HDMI_PICTURE_ASPECT_16_9 << 4;
}
+ if (avi_if.body.avi.VIC) {
+ /* colorimetry: Sections 5.1 and 5.2 of CEA 861-D spec */
+ if ((adjusted_mode->vdisplay == 480) ||
+ (adjusted_mode->vdisplay == 576) ||
+ (adjusted_mode->vdisplay == 240) ||
+ (adjusted_mode->vdisplay == 288)) {
+ avi_if.body.avi.C_M_R |= DIP_AVI_COLOR_ITU601;
+ } else if ((adjusted_mode->vdisplay == 720) ||
+ (adjusted_mode->vdisplay == 1080)) {
+ avi_if.body.avi.C_M_R |= DIP_AVI_COLOR_ITU709;
+ }
+ }
+
+ avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_IT_CONTENT;
+
intel_set_infoframe(encoder, &avi_if);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 3/3] [VPG HSW-A] drm/i915: Populate all fields of AVI infoframe
2013-08-15 4:59 ` [PATCH 3/3] [VPG HSW-A] drm/i915: Populate all fields of " vandana.kannan
@ 2013-08-15 7:43 ` Ville Syrjälä
0 siblings, 0 replies; 10+ messages in thread
From: Ville Syrjälä @ 2013-08-15 7:43 UTC (permalink / raw)
To: vandana.kannan; +Cc: dri-devel
On Thu, Aug 15, 2013 at 10:29:03AM +0530, vandana.kannan@intel.com wrote:
> From: vkannan <vandana.kannan@intel.com>
>
> Populate bar information, colorimetry, IT content, quantization range fields
> of AVI infoframe based on CEA 861-D spec.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_drv.h | 4 ++++
> drivers/gpu/drm/i915/intel_hdmi.c | 39 +++++++++++++++++++++++++++++++++++--
> 2 files changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 97df85d..e02c442 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -412,6 +412,10 @@ struct cxsr_latency {
> #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
> #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
> #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
> +#define DIP_AVI_IT_CONTENT (1 << 7)
> +#define DIP_AVI_BAR_BOTH (3 << 2)
> +#define DIP_AVI_COLOR_ITU601 (1 << 6)
> +#define DIP_AVI_COLOR_ITU709 (2 << 6)
>
> #define DIP_TYPE_SPD 0x83
> #define DIP_VERSION_SPD 0x1
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 7cf6fc5..dbbc02b 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -340,9 +340,22 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
> .type = DIP_TYPE_AVI,
> .ver = DIP_VERSION_AVI,
> .len = DIP_LEN_AVI,
> + .body.avi.Y_A_B_S = 0,
> .body.avi.C_M_R = 8,
> + .body.avi.ITC_EC_Q_SC = 0,
> + .body.avi.VIC = 0,
> + .body.avi.YQ_CN_PR = 0,
> + .body.avi.top_bar_end = 0,
> + .body.avi.bottom_bar_start = 0,
> + .body.avi.left_bar_end = 0,
> + .body.avi.right_bar_start = 0,
This is not needed. All the members not explicitly initialized are
initialized to 0 implicitly.
> };
>
> + /* Bar information */
> + avi_if.body.avi.Y_A_B_S |= DIP_AVI_BAR_BOTH;
Now you're sending bars left/right/top/bottom=0 bars. AFAICS that
would indicate that the entire picture is made of of the bottom and
right bars, ie. no actual content in the picture.
> +
> + avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
> +
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
>
> @@ -351,10 +364,17 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
> avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
> else
> avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
> + } else {
> + /* Set full range quantization for non-CEA modes
> + and 640x480 */
> + if ((avi_if.body.avi.VIC == 0) || (avi_if.body.avi.VIC == 1))
> + avi_if.body.avi.ITC_EC_Q_SC |=
> + DIP_AVI_RGB_QUANT_RANGE_FULL;
> + else
> + avi_if.body.avi.ITC_EC_Q_SC |=
> + DIP_AVI_RGB_QUANT_RANGE_LIMITED;
> }
The spec says we shouldn't send the quantization range unless the QS bit
in EDID CEA block is 1. Now you're sending it anyway. What's the deal?
>
> - avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
> -
> /*If picture aspect ratio (PAR) is set to custom value, then use that,
> else if VIC > 1, then get PAR from CEA mode list, else, calculate
> PAR based on resolution */
> @@ -377,6 +397,21 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
> avi_if.body.avi.C_M_R |= HDMI_PICTURE_ASPECT_16_9 << 4;
> }
>
> + if (avi_if.body.avi.VIC) {
> + /* colorimetry: Sections 5.1 and 5.2 of CEA 861-D spec */
> + if ((adjusted_mode->vdisplay == 480) ||
> + (adjusted_mode->vdisplay == 576) ||
> + (adjusted_mode->vdisplay == 240) ||
> + (adjusted_mode->vdisplay == 288)) {
> + avi_if.body.avi.C_M_R |= DIP_AVI_COLOR_ITU601;
> + } else if ((adjusted_mode->vdisplay == 720) ||
> + (adjusted_mode->vdisplay == 1080)) {
> + avi_if.body.avi.C_M_R |= DIP_AVI_COLOR_ITU709;
> + }
> + }
We're outputting RGB data only, so we should not set the colorimetry bits.
When we decide to implement better colorspace support, we're again going
to need some new properties to let the user set the colorimetry
appropriately.
> +
> + avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_IT_CONTENT;
> +
> intel_set_infoframe(encoder, &avi_if);
> }
>
> --
> 1.7.9.5
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode
2013-08-15 4:59 [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode vandana.kannan
2013-08-15 4:59 ` [PATCH 2/3] [VPG HSW-A] drm/i915: Add PAR support in AVI infoframe vandana.kannan
2013-08-15 4:59 ` [PATCH 3/3] [VPG HSW-A] drm/i915: Populate all fields of " vandana.kannan
@ 2013-08-15 7:06 ` Ville Syrjälä
2013-08-15 8:13 ` Daniel Vetter
` (2 more replies)
2 siblings, 3 replies; 10+ messages in thread
From: Ville Syrjälä @ 2013-08-15 7:06 UTC (permalink / raw)
To: vandana.kannan; +Cc: dri-devel
On Thu, Aug 15, 2013 at 10:29:01AM +0530, vandana.kannan@intel.com wrote:
> From: vkannan <vandana.kannan@intel.com>
>
> Mode is the video format, which is the information the sink needs to
> properly display an image. a complete definition of video format includes
> video timing, picture aspect ratio, color space, quantization range,
> component depth.
>
> video format timing may be associated with more than 1 video format
> for example, 720x480p formatted in the 4:3 Picture Aspect Ratio or a
> 720x480p formatted in the 16:9 Picture Aspect Ratio.
>
> For HDMI compliance, a set of CEA modes are tested (CEA 861-D table 3).
> This list has 64 modes. When one of the modes are set, the corresponding
> fields should show up correctly (as mentioned in Table 3 of CEA spec).
> For picture aspect ratio, if the mode is found from the CEA mode list,
> the corresponding PAR is sent as part of infoframe. If the mode to be set
> is not part of the CEA mode list, PAR is calculated from resolution.
>
> CEA modes have a specific picture aspect ratio. Adding this field
> as part of drm_display_mode. This is required to be sent as part of AVI
> infoframe for HDMI compliance.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/drm_edid.c | 374 ++++++++++++++++++-------------
> drivers/gpu/drm/gma500/oaktrail_lvds.c | 14 +-
> drivers/gpu/drm/gma500/psb_intel_sdvo.c | 38 ++--
> drivers/gpu/drm/i915/intel_display.c | 3 +-
> drivers/gpu/drm/i915/intel_sdvo.c | 38 ++--
> include/drm/drm_crtc.h | 7 +-
> 6 files changed, 265 insertions(+), 209 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index e8d17ee..83e2fda 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -135,378 +135,379 @@ static const struct drm_display_mode drm_dmt_modes[] = {
> /* 640x350@85Hz */
> { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
> 736, 832, 0, 350, 382, 385, 445, 0,
> - DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
> + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
<snip a lot of the same>
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 9779ea1..07c0d58 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -30,6 +30,7 @@
> #include <linux/types.h>
> #include <linux/idr.h>
> #include <linux/fb.h>
> +#include <linux/hdmi.h>
> #include <drm/drm_mode.h>
>
> #include <drm/drm_fourcc.h>
> @@ -115,12 +116,14 @@ enum drm_mode_status {
> #define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \
> DRM_MODE_TYPE_CRTC_C)
>
> -#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \
> +#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f, \
> + ar) \
> .name = nm, .status = 0, .type = (t), .clock = (c), \
> .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
> .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
> .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
> .vscan = (vs), .flags = (f), \
> + .picture_aspect_ratio = (ar), \
> .base.type = DRM_MODE_OBJECT_MODE
>
> #define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */
> @@ -177,6 +180,8 @@ struct drm_display_mode {
>
> int vrefresh; /* in Hz */
> int hsync; /* in kHz */
> +
> + enum hdmi_picture_aspect picture_aspect_ratio;
> };
I'm not sure we want to bloat drm_display_mode with additional
junk for the sake of CEA modes. We could perhaps just have a
separate VIC indexed array for the aspect ratio information.
At the very least we don't want to modify DRM_MODE() since that makes
this patch needlessly large, and makes DRM_MODE() even harder to decode
for humans. Instead you can just use c99 initializers and do it like so:
{ DRM_MODE(...),
.picture_aspect_ratio = x },
>
> enum drm_connector_status {
> --
> 1.7.9.5
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode
2013-08-15 7:06 ` [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode Ville Syrjälä
@ 2013-08-15 8:13 ` Daniel Vetter
2013-12-18 12:53 ` Vandana Kannan
2013-12-18 13:02 ` Vandana Kannan
2 siblings, 0 replies; 10+ messages in thread
From: Daniel Vetter @ 2013-08-15 8:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: vandana.kannan, dri-devel
On Thu, Aug 15, 2013 at 10:06:42AM +0300, Ville Syrjälä wrote:
> On Thu, Aug 15, 2013 at 10:29:01AM +0530, vandana.kannan@intel.com wrote:
> > From: vkannan <vandana.kannan@intel.com>
> >
> > Mode is the video format, which is the information the sink needs to
> > properly display an image. a complete definition of video format includes
> > video timing, picture aspect ratio, color space, quantization range,
> > component depth.
> >
> > video format timing may be associated with more than 1 video format
> > for example, 720x480p formatted in the 4:3 Picture Aspect Ratio or a
> > 720x480p formatted in the 16:9 Picture Aspect Ratio.
> >
> > For HDMI compliance, a set of CEA modes are tested (CEA 861-D table 3).
> > This list has 64 modes. When one of the modes are set, the corresponding
> > fields should show up correctly (as mentioned in Table 3 of CEA spec).
> > For picture aspect ratio, if the mode is found from the CEA mode list,
> > the corresponding PAR is sent as part of infoframe. If the mode to be set
> > is not part of the CEA mode list, PAR is calculated from resolution.
> >
> > CEA modes have a specific picture aspect ratio. Adding this field
> > as part of drm_display_mode. This is required to be sent as part of AVI
> > infoframe for HDMI compliance.
>
> >
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Slight meta comment: When doing patches which also change code outside of
drm/i915 Please try really hard to split it up into a drm core patch to
prepare things. That patch needs a drm/<something>: prefix so that people
on the mailing list notice that it's not just for drm/i915. Then roll out
the change accross all drivers in a set of drm/<driver>: patches.
Also drm core patches always need to be cc'ed to the dri-devel mailing
list, but drm/i915 should also be cc'ed to the intel-gfx mailing list.
And like Ville mentioned we've recently switched to the shared hdmi
infoframe helpers, so this needs to be rebased on top of
drm-intel-nightly.
Thanks, Daniel
> > ---
> > drivers/gpu/drm/drm_edid.c | 374 ++++++++++++++++++-------------
> > drivers/gpu/drm/gma500/oaktrail_lvds.c | 14 +-
> > drivers/gpu/drm/gma500/psb_intel_sdvo.c | 38 ++--
> > drivers/gpu/drm/i915/intel_display.c | 3 +-
> > drivers/gpu/drm/i915/intel_sdvo.c | 38 ++--
> > include/drm/drm_crtc.h | 7 +-
> > 6 files changed, 265 insertions(+), 209 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index e8d17ee..83e2fda 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -135,378 +135,379 @@ static const struct drm_display_mode drm_dmt_modes[] = {
> > /* 640x350@85Hz */
> > { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
> > 736, 832, 0, 350, 382, 385, 445, 0,
> > - DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
> > + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
> <snip a lot of the same>
> > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> > index 9779ea1..07c0d58 100644
> > --- a/include/drm/drm_crtc.h
> > +++ b/include/drm/drm_crtc.h
> > @@ -30,6 +30,7 @@
> > #include <linux/types.h>
> > #include <linux/idr.h>
> > #include <linux/fb.h>
> > +#include <linux/hdmi.h>
> > #include <drm/drm_mode.h>
> >
> > #include <drm/drm_fourcc.h>
> > @@ -115,12 +116,14 @@ enum drm_mode_status {
> > #define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \
> > DRM_MODE_TYPE_CRTC_C)
> >
> > -#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \
> > +#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f, \
> > + ar) \
> > .name = nm, .status = 0, .type = (t), .clock = (c), \
> > .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
> > .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
> > .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
> > .vscan = (vs), .flags = (f), \
> > + .picture_aspect_ratio = (ar), \
> > .base.type = DRM_MODE_OBJECT_MODE
> >
> > #define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */
> > @@ -177,6 +180,8 @@ struct drm_display_mode {
> >
> > int vrefresh; /* in Hz */
> > int hsync; /* in kHz */
> > +
> > + enum hdmi_picture_aspect picture_aspect_ratio;
> > };
>
> I'm not sure we want to bloat drm_display_mode with additional
> junk for the sake of CEA modes. We could perhaps just have a
> separate VIC indexed array for the aspect ratio information.
>
> At the very least we don't want to modify DRM_MODE() since that makes
> this patch needlessly large, and makes DRM_MODE() even harder to decode
> for humans. Instead you can just use c99 initializers and do it like so:
>
> { DRM_MODE(...),
> .picture_aspect_ratio = x },
>
> >
> > enum drm_connector_status {
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode
2013-08-15 7:06 ` [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode Ville Syrjälä
2013-08-15 8:13 ` Daniel Vetter
@ 2013-12-18 12:53 ` Vandana Kannan
2013-12-18 13:02 ` Vandana Kannan
2 siblings, 0 replies; 10+ messages in thread
From: Vandana Kannan @ 2013-12-18 12:53 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: dri-devel@lists.freedesktop.org
On Aug-15-2013 12:36 PM, Ville Syrjälä wrote:
> On Thu, Aug 15, 2013 at 10:29:01AM +0530, vandana.kannan@intel.com wrote:
>> From: vkannan <vandana.kannan@intel.com>
>>
>> Mode is the video format, which is the information the sink needs to
>> properly display an image. a complete definition of video format includes
>> video timing, picture aspect ratio, color space, quantization range,
>> component depth.
>>
>> video format timing may be associated with more than 1 video format
>> for example, 720x480p formatted in the 4:3 Picture Aspect Ratio or a
>> 720x480p formatted in the 16:9 Picture Aspect Ratio.
>>
>> For HDMI compliance, a set of CEA modes are tested (CEA 861-D table 3).
>> This list has 64 modes. When one of the modes are set, the corresponding
>> fields should show up correctly (as mentioned in Table 3 of CEA spec).
>> For picture aspect ratio, if the mode is found from the CEA mode list,
>> the corresponding PAR is sent as part of infoframe. If the mode to be set
>> is not part of the CEA mode list, PAR is calculated from resolution.
>>
>> CEA modes have a specific picture aspect ratio. Adding this field
>> as part of drm_display_mode. This is required to be sent as part of AVI
>> infoframe for HDMI compliance.
>
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> ---
>> drivers/gpu/drm/drm_edid.c | 374 ++++++++++++++++++-------------
>> drivers/gpu/drm/gma500/oaktrail_lvds.c | 14 +-
>> drivers/gpu/drm/gma500/psb_intel_sdvo.c | 38 ++--
>> drivers/gpu/drm/i915/intel_display.c | 3 +-
>> drivers/gpu/drm/i915/intel_sdvo.c | 38 ++--
>> include/drm/drm_crtc.h | 7 +-
>> 6 files changed, 265 insertions(+), 209 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index e8d17ee..83e2fda 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -135,378 +135,379 @@ static const struct drm_display_mode drm_dmt_modes[] = {
>> /* 640x350@85Hz */
>> { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
>> 736, 832, 0, 350, 382, 385, 445, 0,
>> - DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
>> + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
> <snip a lot of the same>
>> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
>> index 9779ea1..07c0d58 100644
>> --- a/include/drm/drm_crtc.h
>> +++ b/include/drm/drm_crtc.h
>> @@ -30,6 +30,7 @@
>> #include <linux/types.h>
>> #include <linux/idr.h>
>> #include <linux/fb.h>
>> +#include <linux/hdmi.h>
>> #include <drm/drm_mode.h>
>>
>> #include <drm/drm_fourcc.h>
>> @@ -115,12 +116,14 @@ enum drm_mode_status {
>> #define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \
>> DRM_MODE_TYPE_CRTC_C)
>>
>> -#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \
>> +#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f, \
>> + ar) \
>> .name = nm, .status = 0, .type = (t), .clock = (c), \
>> .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
>> .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
>> .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
>> .vscan = (vs), .flags = (f), \
>> + .picture_aspect_ratio = (ar), \
>> .base.type = DRM_MODE_OBJECT_MODE
>>
>> #define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */
>> @@ -177,6 +180,8 @@ struct drm_display_mode {
>>
>> int vrefresh; /* in Hz */
>> int hsync; /* in kHz */
>> +
>> + enum hdmi_picture_aspect picture_aspect_ratio;
>> };
>
> I'm not sure we want to bloat drm_display_mode with additional
> junk for the sake of CEA modes. We could perhaps just have a
> separate VIC indexed array for the aspect ratio information.
>
> At the very least we don't want to modify DRM_MODE() since that makes
> this patch needlessly large, and makes DRM_MODE() even harder to decode
> for humans. Instead you can just use c99 initializers and do it like so:
>
> { DRM_MODE(...),
> .picture_aspect_ratio = x },
>
>>
>> enum drm_connector_status {
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
I am working on making changes such that cea_modes looks like
{ DRM_MODE(...),
.picture_aspect_ratio = x },
Will push the patch soon. Please let me know if there are any concerns.
-Vandana
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode
2013-08-15 7:06 ` [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode Ville Syrjälä
2013-08-15 8:13 ` Daniel Vetter
2013-12-18 12:53 ` Vandana Kannan
@ 2013-12-18 13:02 ` Vandana Kannan
2013-12-18 13:10 ` Daniel Vetter
2 siblings, 1 reply; 10+ messages in thread
From: Vandana Kannan @ 2013-12-18 13:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx@lists.freedesktop.org
On Aug-15-2013 12:36 PM, Ville Syrjälä wrote:
> On Thu, Aug 15, 2013 at 10:29:01AM +0530, vandana.kannan@intel.com wrote:
>> From: vkannan <vandana.kannan@intel.com>
>>
>> Mode is the video format, which is the information the sink needs to
>> properly display an image. a complete definition of video format includes
>> video timing, picture aspect ratio, color space, quantization range,
>> component depth.
>>
>> video format timing may be associated with more than 1 video format
>> for example, 720x480p formatted in the 4:3 Picture Aspect Ratio or a
>> 720x480p formatted in the 16:9 Picture Aspect Ratio.
>>
>> For HDMI compliance, a set of CEA modes are tested (CEA 861-D table 3).
>> This list has 64 modes. When one of the modes are set, the corresponding
>> fields should show up correctly (as mentioned in Table 3 of CEA spec).
>> For picture aspect ratio, if the mode is found from the CEA mode list,
>> the corresponding PAR is sent as part of infoframe. If the mode to be set
>> is not part of the CEA mode list, PAR is calculated from resolution.
>>
>> CEA modes have a specific picture aspect ratio. Adding this field
>> as part of drm_display_mode. This is required to be sent as part of AVI
>> infoframe for HDMI compliance.
>
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> ---
>> drivers/gpu/drm/drm_edid.c | 374 ++++++++++++++++++-------------
>> drivers/gpu/drm/gma500/oaktrail_lvds.c | 14 +-
>> drivers/gpu/drm/gma500/psb_intel_sdvo.c | 38 ++--
>> drivers/gpu/drm/i915/intel_display.c | 3 +-
>> drivers/gpu/drm/i915/intel_sdvo.c | 38 ++--
>> include/drm/drm_crtc.h | 7 +-
>> 6 files changed, 265 insertions(+), 209 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index e8d17ee..83e2fda 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -135,378 +135,379 @@ static const struct drm_display_mode drm_dmt_modes[] = {
>> /* 640x350@85Hz */
>> { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
>> 736, 832, 0, 350, 382, 385, 445, 0,
>> - DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
>> + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 0) },
> <snip a lot of the same>
>> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
>> index 9779ea1..07c0d58 100644
>> --- a/include/drm/drm_crtc.h
>> +++ b/include/drm/drm_crtc.h
>> @@ -30,6 +30,7 @@
>> #include <linux/types.h>
>> #include <linux/idr.h>
>> #include <linux/fb.h>
>> +#include <linux/hdmi.h>
>> #include <drm/drm_mode.h>
>>
>> #include <drm/drm_fourcc.h>
>> @@ -115,12 +116,14 @@ enum drm_mode_status {
>> #define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \
>> DRM_MODE_TYPE_CRTC_C)
>>
>> -#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \
>> +#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f, \
>> + ar) \
>> .name = nm, .status = 0, .type = (t), .clock = (c), \
>> .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
>> .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
>> .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
>> .vscan = (vs), .flags = (f), \
>> + .picture_aspect_ratio = (ar), \
>> .base.type = DRM_MODE_OBJECT_MODE
>>
>> #define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */
>> @@ -177,6 +180,8 @@ struct drm_display_mode {
>>
>> int vrefresh; /* in Hz */
>> int hsync; /* in kHz */
>> +
>> + enum hdmi_picture_aspect picture_aspect_ratio;
>> };
>
> I'm not sure we want to bloat drm_display_mode with additional
> junk for the sake of CEA modes. We could perhaps just have a
> separate VIC indexed array for the aspect ratio information.
>
> At the very least we don't want to modify DRM_MODE() since that makes
> this patch needlessly large, and makes DRM_MODE() even harder to decode
> for humans. Instead you can just use c99 initializers and do it like so:
>
> { DRM_MODE(...),
> .picture_aspect_ratio = x },
>
>>
>> enum drm_connector_status {
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
I am working on making changes such that cea_modes looks like
{ DRM_MODE(...),
.picture_aspect_ratio = x },
Will push the patch soon. Please let me know if there are any concerns.
-Vandana
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode
2013-12-18 13:02 ` Vandana Kannan
@ 2013-12-18 13:10 ` Daniel Vetter
0 siblings, 0 replies; 10+ messages in thread
From: Daniel Vetter @ 2013-12-18 13:10 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx@lists.freedesktop.org, dri-devel
Re-adding dri-devel.
On Wed, Dec 18, 2013 at 2:02 PM, Vandana Kannan
<vandana.kannan@intel.com> wrote:
>>> @@ -177,6 +180,8 @@ struct drm_display_mode {
>>>
>>> int vrefresh; /* in Hz */
>>> int hsync; /* in kHz */
>>> +
>>> + enum hdmi_picture_aspect picture_aspect_ratio;
>>> };
>>
>> I'm not sure we want to bloat drm_display_mode with additional
>> junk for the sake of CEA modes. We could perhaps just have a
>> separate VIC indexed array for the aspect ratio information.
>>
>> At the very least we don't want to modify DRM_MODE() since that makes
>> this patch needlessly large, and makes DRM_MODE() even harder to decode
>> for humans. Instead you can just use c99 initializers and do it like so:
>>
>> { DRM_MODE(...),
>> .picture_aspect_ratio = x },
> I am working on making changes such that cea_modes looks like
> { DRM_MODE(...),
> .picture_aspect_ratio = x },
> Will push the patch soon. Please let me know if there are any concerns.
Ville's on vacation, but imo this makes sense. Also wrt process when
doing core drm changes (i.e. anything touching files outside of
drm/i915) then please always cross-post to dri-devel for discussions
and patches.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2013-12-18 13:10 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-08-15 4:59 [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode vandana.kannan
2013-08-15 4:59 ` [PATCH 2/3] [VPG HSW-A] drm/i915: Add PAR support in AVI infoframe vandana.kannan
2013-08-15 7:32 ` Ville Syrjälä
2013-08-15 4:59 ` [PATCH 3/3] [VPG HSW-A] drm/i915: Populate all fields of " vandana.kannan
2013-08-15 7:43 ` Ville Syrjälä
2013-08-15 7:06 ` [PATCH 1/3] [VPG HSW-A] drm/i915: Add aspect ratio in drm_display_mode Ville Syrjälä
2013-08-15 8:13 ` Daniel Vetter
2013-12-18 12:53 ` Vandana Kannan
2013-12-18 13:02 ` Vandana Kannan
2013-12-18 13:10 ` Daniel Vetter
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.