From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] i915: Update VGA arbiter support for newer devices Date: Fri, 16 Aug 2013 13:20:17 +0300 Message-ID: <20130816102017.GK7159@intel.com> References: <20130815223917.27890.28003.stgit@bling.home> <1376607255.13642.155.camel@ul30vt.home> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 5734AE7C2F for ; Fri, 16 Aug 2013 03:20:21 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1376607255.13642.155.camel@ul30vt.home> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Alex Williamson Cc: Dave Airlie , "intel-gfx@lists.freedesktop.org" , LKML List-Id: intel-gfx@lists.freedesktop.org On Thu, Aug 15, 2013 at 04:54:15PM -0600, Alex Williamson wrote: > On Fri, 2013-08-16 at 08:49 +1000, Dave Airlie wrote: > > On Fri, Aug 16, 2013 at 8:43 AM, Alex Williamson > > wrote: > > > This is intended to add VGA arbiter support for Intel HD graphics on > > > Core processors. The old GMCH registers no longer exist, so even > > > though it appears that i915 participates in VGA arbitration, it doesn= 't > > > work. On Intel HD graphics we already attempt to disable VGA regions > > > of the device. This makes registering as a VGA client unnecessary si= nce > > > we don't intend to operate differently depending on how many VGA devi= ces > > > are present. We can disable VGA memory regions by clearing a memory > > > enable bit in the VGA MSR. That only leaves VGA IO, which we update > > > the VGA arbiter to know that we don't participate in VGA memory > > > arbitration. We also add a hook on unload to re-enable memory and > > > reinstate VGA memory arbitration. > > = > > I would think there is still a VGA disable bit on the Intel device > > somewhere, we'd just need > > Intel to look in the docs and find it. A bit that can nuke both i/o > > and cmd regs. > = > The only bit available is in the GGC and is a keyed/locked register that > not only disables VGA memory and I/O, but also modifies the class code > of the device. Early Core processors didn't lock this, but it's > untouchable in newer ones AFAICT. Thanks, I've not found anything else in the docs. And also we _need_ VGA I/O access to make i915_disable_vga() work. It's not 100% clear whether we really need to poke at the sequencer register in modern hardware, but the docs do still list it as a mandatory step. So even if we were to have a global "disable VGA I/O and mem bit" we'd need to make sure we already disabled VGA eg. after resume when the BIOS had a chance to turn the VGA display back on. I think there were also some BIOSen that turned VGA display back on when closing/opening the laptop lid. Not sure what would even happen with those if totally disabled VGA I/O access. I'm not sure they actually frob with the VGA regs though. Could be they just turn on the VGA display bit in the VGA_CONTROL register. -- = Ville Syrj=E4l=E4 Intel OTC From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752490Ab3HPKU1 (ORCPT ); Fri, 16 Aug 2013 06:20:27 -0400 Received: from mga09.intel.com ([134.134.136.24]:37440 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751721Ab3HPKUV (ORCPT ); Fri, 16 Aug 2013 06:20:21 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.89,894,1367996400"; d="scan'208";a="388115419" Date: Fri, 16 Aug 2013 13:20:17 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Alex Williamson Cc: Dave Airlie , "intel-gfx@lists.freedesktop.org" , Dave Airlie , LKML Subject: Re: [PATCH] i915: Update VGA arbiter support for newer devices Message-ID: <20130816102017.GK7159@intel.com> References: <20130815223917.27890.28003.stgit@bling.home> <1376607255.13642.155.camel@ul30vt.home> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1376607255.13642.155.camel@ul30vt.home> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 15, 2013 at 04:54:15PM -0600, Alex Williamson wrote: > On Fri, 2013-08-16 at 08:49 +1000, Dave Airlie wrote: > > On Fri, Aug 16, 2013 at 8:43 AM, Alex Williamson > > wrote: > > > This is intended to add VGA arbiter support for Intel HD graphics on > > > Core processors. The old GMCH registers no longer exist, so even > > > though it appears that i915 participates in VGA arbitration, it doesn't > > > work. On Intel HD graphics we already attempt to disable VGA regions > > > of the device. This makes registering as a VGA client unnecessary since > > > we don't intend to operate differently depending on how many VGA devices > > > are present. We can disable VGA memory regions by clearing a memory > > > enable bit in the VGA MSR. That only leaves VGA IO, which we update > > > the VGA arbiter to know that we don't participate in VGA memory > > > arbitration. We also add a hook on unload to re-enable memory and > > > reinstate VGA memory arbitration. > > > > I would think there is still a VGA disable bit on the Intel device > > somewhere, we'd just need > > Intel to look in the docs and find it. A bit that can nuke both i/o > > and cmd regs. > > The only bit available is in the GGC and is a keyed/locked register that > not only disables VGA memory and I/O, but also modifies the class code > of the device. Early Core processors didn't lock this, but it's > untouchable in newer ones AFAICT. Thanks, I've not found anything else in the docs. And also we _need_ VGA I/O access to make i915_disable_vga() work. It's not 100% clear whether we really need to poke at the sequencer register in modern hardware, but the docs do still list it as a mandatory step. So even if we were to have a global "disable VGA I/O and mem bit" we'd need to make sure we already disabled VGA eg. after resume when the BIOS had a chance to turn the VGA display back on. I think there were also some BIOSen that turned VGA display back on when closing/opening the laptop lid. Not sure what would even happen with those if totally disabled VGA I/O access. I'm not sure they actually frob with the VGA regs though. Could be they just turn on the VGA display bit in the VGA_CONTROL register. -- Ville Syrjälä Intel OTC