diff for duplicates of <201308172128.35245.arnd@arndb.de> diff --git a/a/1.txt b/N1/1.txt index cb4f713..d2eeed5 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,18 +1,18 @@ On Friday 16 August 2013, Sebastian Hesselbarth wrote: -> + cpu at 0 { +> + cpu@0 { > + compatible = "marvell,sheeva-v7"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <0>; > + }; ... -> + l2: l2-cache-controller at 1ac0000 { +> + l2: l2-cache-controller@1ac0000 { > + compatible = "marvell,aurora-outer-cache"; > + reg = <0x1ac0000 0x1000>; > + cache-level = <2>; > + }; > + -> + gic: interrupt-controller at 1ad0000 { +> + gic: interrupt-controller@1ad0000 { > + compatible = "arm,cortex-a9-gic"; > + reg = <0x1ad1000 0x1000 > + 0x1ad0100 0x0100>; @@ -20,7 +20,7 @@ On Friday 16 August 2013, Sebastian Hesselbarth wrote: > + #interrupt-cells = <3>; > + }; > + -> + local-timer at 1ad0600 { +> + local-timer@1ad0600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0x1ad0600 0x20>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N1/content_digest index ea4ad29..744da5b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,26 +1,39 @@ "ref\01376682098-10580-1-git-send-email-sebastian.hesselbarth@gmail.com\0" "ref\01376682098-10580-5-git-send-email-sebastian.hesselbarth@gmail.com\0" - "From\0arnd@arndb.de (Arnd Bergmann)\0" - "Subject\0[RFC v1 4/5] ARM: mvebu: add Armada 1500 and Sony NSZ-GS7 device tree files\0" + "From\0Arnd Bergmann <arnd@arndb.de>\0" + "Subject\0Re: [RFC v1 4/5] ARM: mvebu: add Armada 1500 and Sony NSZ-GS7 device tree files\0" "Date\0Sat, 17 Aug 2013 21:28:34 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" + "Cc\0Rob Herring <rob.herring@calxeda.com>" + Pawel Moll <pawel.moll@arm.com> + Mark Rutland <mark.rutland@arm.com> + Stephen Warren <swarren@wwwdotorg.org> + Ian Campbell <ian.campbell@citrix.com> + Russell King <linux@arm.linux.org.uk> + Jason Cooper <jason@lakedaemon.net> + Andrew Lunn <andrew@lunn.ch> + Gregory Clement <gregory.clement@free-electrons.com> + Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + devicetree@vger.kernel.org + linux-arm-kernel@lists.infradead.org + " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" "On Friday 16 August 2013, Sebastian Hesselbarth wrote:\n" - "> + cpu at 0 {\n" + "> + cpu@0 {\n" "> + compatible = \"marvell,sheeva-v7\";\n" "> + device_type = \"cpu\";\n" "> + next-level-cache = <&l2>;\n" "> + reg = <0>;\n" "> + };\n" "...\n" - "> + l2: l2-cache-controller at 1ac0000 {\n" + "> + l2: l2-cache-controller@1ac0000 {\n" "> + compatible = \"marvell,aurora-outer-cache\";\n" "> + reg = <0x1ac0000 0x1000>;\n" "> + cache-level = <2>;\n" "> + };\n" "> +\n" - "> + gic: interrupt-controller at 1ad0000 {\n" + "> + gic: interrupt-controller@1ad0000 {\n" "> + compatible = \"arm,cortex-a9-gic\";\n" "> + reg = <0x1ad1000 0x1000\n" "> + 0x1ad0100 0x0100>;\n" @@ -28,7 +41,7 @@ "> + #interrupt-cells = <3>;\n" "> + };\n" "> +\n" - "> + local-timer at 1ad0600 {\n" + "> + local-timer@1ad0600 {\n" "> + compatible = \"arm,cortex-a9-twd-timer\";\n" "> + reg = <0x1ad0600 0x20>;\n" "> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -41,4 +54,4 @@ "\n" "\tArnd" -f6b799b835f4b344b0ababb686b33a063274b8d9683fbe8d2f36d1fa4952f37c +90c6a9871a261bd6a329388370fbc4f913c2b7bd37c8f0f250dff18db6f5f894
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