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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, yogesh.mohan.marimuthu@intel.com
Subject: Re: [PATCH v2 03/15] drm/i915: add VLV pipeconf bit definition for DSI PLL lock
Date: Tue, 20 Aug 2013 17:12:04 +0300	[thread overview]
Message-ID: <20130820141204.GU7159@intel.com> (raw)
In-Reply-To: <ef6ccd0d07c6c1ae89d56fda1cff86c96cb16c2f.1376655793.git.jani.nikula@intel.com>

On Fri, Aug 16, 2013 at 03:35:51PM +0300, Jani Nikula wrote:
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b417a8c..2f8e341 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2972,6 +2972,7 @@
>  #define   PIPECONF_DISABLE	0
>  #define   PIPECONF_DOUBLE_WIDE	(1<<30)
>  #define   I965_PIPECONF_ACTIVE	(1<<30)
> +#define   PIPECONF_DSI_PLL_LOCKED	(1<<29) /* vlv only */

Maybe add a comment that it's only in the pipe A register
(at least according to spec).

>  #define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
>  #define   PIPECONF_SINGLE_WIDE	0
>  #define   PIPECONF_PIPE_UNLOCKED 0
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

  reply	other threads:[~2013-08-20 14:12 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-08-16 12:35 [PATCH v2 00/15] drm/i915: Baytrail MIPI DSI support Jani Nikula
2013-08-16 12:35 ` [PATCH v2 01/15] drm: add MIPI DSI encoder and connector types Jani Nikula
2013-08-20 12:05   ` [PATCH] " Jani Nikula
2013-08-16 12:35 ` [PATCH v2 02/15] drm/i915: add more VLV IOSF sideband ports accessors Jani Nikula
2013-08-16 12:35 ` [PATCH v2 03/15] drm/i915: add VLV pipeconf bit definition for DSI PLL lock Jani Nikula
2013-08-20 14:12   ` Ville Syrjälä [this message]
2013-08-16 12:35 ` [PATCH v2 04/15] drm/i915: add MIPI DSI register definitions Jani Nikula
2013-08-16 12:35 ` [PATCH v2 05/15] drm/i915: add MIPI DSI output type and subtypes Jani Nikula
2013-08-16 12:35 ` [PATCH v2 06/15] drm/i915: add structs for MIPI DSI output Jani Nikula
2013-08-16 12:35 ` [PATCH v2 07/15] drm/i915: add MIPI DSI command sending routines Jani Nikula
2013-08-20 14:13   ` Ville Syrjälä
2013-08-16 12:35 ` [PATCH v2 08/15] drm/i915: add basic MIPI DSI output support Jani Nikula
2013-08-20 14:23   ` Ville Syrjälä
2013-08-16 12:35 ` [PATCH v2 09/15] drm/i915: add VLV DSI PLL Calculations Jani Nikula
2013-08-20 18:35   ` Ville Syrjälä
2013-08-16 12:35 ` [PATCH v2 10/15] drm/i915: fix PLL assertions for DSI PLL Jani Nikula
2013-08-16 12:35 ` [PATCH v2 11/15] drm/i915: don't enable DPLL for DSI Jani Nikula
2013-08-16 12:36 ` [PATCH v2 12/15] drm/i915: Band Gap WA Jani Nikula
2013-08-23 16:21   ` Ville Syrjälä
2013-08-16 12:36 ` [PATCH v2 13/15] drm/i915: Parse the MIPI related VBT Block and store relevant info Jani Nikula
2013-08-16 12:36 ` [PATCH v2 14/15] drm/i915: initialize DSI output on VLV Jani Nikula
2013-08-16 12:36 ` [PATCH v2 15/15] drm/i915: add AUO MIPI DSI display sub-encoder Jani Nikula

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