From: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
To: Ritesh Harjani <ritesh.harjani@gmail.com>
Cc: David Ahern <dsahern@gmail.com>,
Michael Ellerman <michael@ellerman.id.au>,
Manuel Selva <selva.manuel@gmail.com>,
linux-perf-users@vger.kernel.org
Subject: Re: How does perf collects stats for L1/L2 cache events
Date: Fri, 23 Aug 2013 13:23:55 -0300 [thread overview]
Message-ID: <20130823162355.GA1895@ghostprotocols.net> (raw)
In-Reply-To: <CAD15agZimrkEsYi12oQRSCjTvNaXd9rFzrPE=tRBkqJiASUJ=A@mail.gmail.com>
Em Fri, Aug 23, 2013 at 04:21:00PM +0530, Ritesh Harjani escreveu:
> Hi folks,
>
> I have some following queries on perf:
>
> 1. how does perf collect L1/L2 cache events on various architectures?
PMU counters.
> 2. My question might be specific to ARM architecture as well, does perf
> collects the stats of cache events based on PMU counter in ARM processor ?
yes
> If no, could some one please tell, how does perf collects this data ?
>
> 3. And how about rest of the architectures ?
PMU counters. Look at arch/
> 4. Also, If possible could someone please guide to that piece of code(
> where cache events stats are collected ) in tools/perf/ ?
Start at arch/arm, I hadn't looked, but did a quick scan now with:
[acme@zoo linux]$ find arch/arm/ -name "*perf*"
- Arnaldo
parent reply other threads:[~2013-08-23 16:24 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <CAD15agZimrkEsYi12oQRSCjTvNaXd9rFzrPE=tRBkqJiASUJ=A@mail.gmail.com>]
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