Re: [Qemu-devel] [PATCH 4/4] tcg: Constant fold div, rem

[Aurelien Jarno <aurelien@aurel32.net>]

On Sat, Aug 17, 2013 at 04:26:46PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/optimize.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index e8dedf3..b29bf25 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -304,6 +304,25 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
>          muls64(&l64, &h64, x, y);
>          return h64;
>  
> +    case INDEX_op_div_i32:
> +        /* Avoid crashing on divide by zero, otherwise undefined.  */
> +        return (int32_t)x / ((int32_t)y ? : 1);
> +    case INDEX_op_divu_i32:
> +        return (uint32_t)x / ((uint32_t)y ? : 1);
> +    case INDEX_op_div_i64:
> +        return (int64_t)x / ((int64_t)y ? : 1);
> +    case INDEX_op_divu_i64:
> +        return (uint64_t)x / ((uint64_t)y ? : 1);
> +
> +    case INDEX_op_rem_i32:
> +        return (int32_t)x % ((int32_t)y ? : 1);
> +    case INDEX_op_remu_i32:
> +        return (uint32_t)x % ((uint32_t)y ? : 1);
> +    case INDEX_op_rem_i64:
> +        return (int64_t)x % ((int64_t)y ? : 1);
> +    case INDEX_op_remu_i64:
> +        return (uint64_t)x % ((uint64_t)y ? : 1);
> +
>      default:
>          fprintf(stderr,
>                  "Unrecognized operation %d in do_constant_folding.\n", op);
> @@ -902,6 +921,10 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr,
>          CASE_OP_32_64(nor):
>          CASE_OP_32_64(muluh):
>          CASE_OP_32_64(mulsh):
> +        CASE_OP_32_64(div):
> +        CASE_OP_32_64(divu):
> +        CASE_OP_32_64(rem):
> +        CASE_OP_32_64(remu):
>              if (temps[args[1]].state == TCG_TEMP_CONST
>                  && temps[args[2]].state == TCG_TEMP_CONST) {
>                  s->gen_opc_buf[op_index] = op_to_movi(op);

This looks fine to me, though I haven't been able to trigger this code
path. So:

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net