From: Aurelien Jarno <aurelien@aurel32.net>
To: Richard Henderson <rth@twiddle.net>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 02/18] tcg: Change flush_icache_range arguments to uintptr_t
Date: Wed, 28 Aug 2013 23:06:14 +0200 [thread overview]
Message-ID: <20130828210614.GF5908@ohm.aurel32.net> (raw)
In-Reply-To: <1377190729-14008-3-git-send-email-rth@twiddle.net>
On Thu, Aug 22, 2013 at 09:58:33AM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/aarch64/tcg-target.h | 3 +--
> tcg/arm/tcg-target.h | 9 ++++-----
> tcg/hppa/tcg-target.h | 3 +--
> tcg/i386/tcg-target.h | 3 +--
> tcg/ia64/tcg-target.h | 3 +--
> tcg/mips/tcg-target.h | 3 +--
> tcg/s390/tcg-target.h | 3 +--
> tcg/sparc/tcg-target.h | 12 ++++--------
> tcg/tcg.c | 6 ++----
> tcg/tci/tcg-target.h | 3 +--
> 10 files changed, 17 insertions(+), 31 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index 51e5092..71f89ed 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -92,8 +92,7 @@ enum {
> TCG_AREG0 = TCG_REG_X19,
> };
>
> -static inline void flush_icache_range(tcg_target_ulong start,
> - tcg_target_ulong stop)
> +static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
> __builtin___clear_cache((char *)start, (char *)stop);
> }
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 5cd9d6a..5637ffe 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -90,15 +90,14 @@ enum {
> TCG_AREG0 = TCG_REG_R6,
> };
>
> -static inline void flush_icache_range(tcg_target_ulong start,
> - tcg_target_ulong stop)
> +static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
> #if QEMU_GNUC_PREREQ(4, 1)
> __builtin___clear_cache((char *) start, (char *) stop);
> #else
> - register unsigned long _beg __asm ("a1") = start;
> - register unsigned long _end __asm ("a2") = stop;
> - register unsigned long _flg __asm ("a3") = 0;
> + register uintptr_t _beg __asm("a1") = start;
> + register uintptr_t _end __asm("a2") = stop;
> + register uintptr_t _flg __asm("a3") = 0;
> __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
> #endif
> }
> diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
> index 25467bd..a9257a5 100644
> --- a/tcg/hppa/tcg-target.h
> +++ b/tcg/hppa/tcg-target.h
> @@ -109,8 +109,7 @@ typedef enum {
> #define TCG_AREG0 TCG_REG_R17
>
>
> -static inline void flush_icache_range(tcg_target_ulong start,
> - tcg_target_ulong stop)
> +static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
> start &= ~31;
> while (start <= stop) {
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index e3f6bb9..963e839 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -135,8 +135,7 @@ typedef enum {
> # define TCG_AREG0 TCG_REG_EBP
> #endif
>
> -static inline void flush_icache_range(tcg_target_ulong start,
> - tcg_target_ulong stop)
> +static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
> }
>
> diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
> index f32d519..428dc40 100644
> --- a/tcg/ia64/tcg-target.h
> +++ b/tcg/ia64/tcg-target.h
> @@ -158,8 +158,7 @@ typedef enum {
>
> #define TCG_AREG0 TCG_REG_R7
>
> -static inline void flush_icache_range(tcg_target_ulong start,
> - tcg_target_ulong stop)
> +static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
> start = start & ~(32UL - 1UL);
> stop = (stop + (32UL - 1UL)) & ~(32UL - 1UL);
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index a438950..433bad0 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -125,8 +125,7 @@ typedef enum {
> #include <sys/cachectl.h>
> #endif
>
> -static inline void flush_icache_range(tcg_target_ulong start,
> - tcg_target_ulong stop)
> +static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
> cacheflush ((void *)start, stop-start, ICACHE);
> }
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index 42ca36c..60ffd7b 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -110,8 +110,7 @@ enum {
> TCG_AREG0 = TCG_REG_R10,
> };
>
> -static inline void flush_icache_range(tcg_target_ulong start,
> - tcg_target_ulong stop)
> +static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
> }
>
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index dab52d7..d1ca2d6 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -138,16 +138,12 @@ typedef enum {
>
> #define TCG_AREG0 TCG_REG_I0
>
> -static inline void flush_icache_range(tcg_target_ulong start,
> - tcg_target_ulong stop)
> +static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
> - unsigned long p;
> -
> - p = start & ~(8UL - 1UL);
> - stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
> -
> - for (; p < stop; p += 8)
> + uintptr_t p;
> + for (p = start & -8; p < (stop + 7) & -8; p += 8) {
> __asm__ __volatile__("flush\t%0" : : "r" (p));
> + }
> }
>
> #endif
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index dac8224..a0d0e9e 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -284,8 +284,7 @@ void tcg_prologue_init(TCGContext *s)
> s->code_buf = s->code_gen_prologue;
> s->code_ptr = s->code_buf;
> tcg_target_qemu_prologue(s);
> - flush_icache_range((tcg_target_ulong)s->code_buf,
> - (tcg_target_ulong)s->code_ptr);
> + flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
>
> #ifdef DEBUG_DISAS
> if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
> @@ -2382,8 +2381,7 @@ int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf)
> tcg_gen_code_common(s, gen_code_buf, -1);
>
> /* flush instruction cache */
> - flush_icache_range((tcg_target_ulong)gen_code_buf,
> - (tcg_target_ulong)s->code_ptr);
> + flush_icache_range((uintptr_t)gen_code_buf, (uintptr_t)s->code_ptr);
>
> return s->code_ptr - gen_code_buf;
> }
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index d7fc14e..c80a34f 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -169,8 +169,7 @@ void tci_disas(uint8_t opc);
> tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
> #define tcg_qemu_tb_exec tcg_qemu_tb_exec
>
> -static inline void flush_icache_range(tcg_target_ulong start,
> - tcg_target_ulong stop)
> +static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
> }
>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2013-08-28 21:06 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-22 16:58 [Qemu-devel] [PATCH 00/18] tcg: decouple tcg_target_long from pointer size Richard Henderson
2013-08-22 16:58 ` [Qemu-devel] [PATCH 01/18] qtest: Fix FMT_timeval vs time_t Richard Henderson
2013-08-22 17:09 ` Andreas Färber
2013-08-22 17:53 ` Richard Henderson
2013-08-22 18:01 ` Andreas Färber
2013-08-22 18:05 ` Richard Henderson
2013-08-22 16:58 ` [Qemu-devel] [PATCH 02/18] tcg: Change flush_icache_range arguments to uintptr_t Richard Henderson
2013-08-28 21:06 ` Aurelien Jarno [this message]
2013-08-22 16:58 ` [Qemu-devel] [PATCH 03/18] tcg: Change tcg_qemu_tb_exec return " Richard Henderson
2013-08-28 21:06 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 04/18] tcg: Fix next_tb type in cpu_exec Richard Henderson
2013-08-28 21:07 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 05/18] tcg: Define TCG_TYPE_PTR properly Richard Henderson
2013-08-29 10:53 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 06/18] tcg: Define TCG_ptr properly Richard Henderson
2013-08-29 10:53 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 07/18] tcg: Change frame pointer offsets to intptr_t Richard Henderson
2013-08-29 10:53 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 08/18] tcg: Change memory " Richard Henderson
2013-08-29 10:53 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 09/18] tcg: Change relocation " Richard Henderson
2013-08-29 10:53 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 10/18] tcg: Use uintptr_t in TCGHelperInfo Richard Henderson
2013-08-29 10:53 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 11/18] tcg: Change tcg_gen_exit_tb argument to uintptr_t Richard Henderson
2013-08-29 10:54 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 12/18] tcg: Change tcg_out_ld/st offset to intptr_t Richard Henderson
2013-08-29 16:44 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 13/18] tcg: Use appropriate types in tcg_reg_alloc_call Richard Henderson
2013-08-29 16:44 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 14/18] tcg: Fix jit debug for pointer size != register size Richard Henderson
2013-08-29 16:44 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 15/18] tcg: Allow TCG_TARGET_REG_BITS to be specified independantly Richard Henderson
2013-08-29 16:45 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 16/18] tcg-i386: Use intptr_t appropriately Richard Henderson
2013-08-29 16:45 ` Aurelien Jarno
2013-08-22 16:58 ` [Qemu-devel] [PATCH 17/18] tcg-i386: Adjust tcg_out_tlb_load for x32 Richard Henderson
2013-08-29 16:45 ` Aurelien Jarno
2013-08-29 17:53 ` Richard Henderson
2013-08-29 20:52 ` Richard Henderson
2013-08-22 16:58 ` [Qemu-devel] [PATCH 18/18] configure: Allow x32 as a host Richard Henderson
2013-08-29 16:45 ` Aurelien Jarno
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